De-interleaving samples with SHARC 21369

Hello all,

Correct me if i'm wrong, but SPORT's DMA is not able to de-interleave
samples when we are in TDM mode ( or I2S actually ), since it's not 2D
capable ?
I can't find any trick that would allow me to de-interleave the
samples while receiving, without using the core, am i missing anything ?

Even worse, it seems that, if i am streaming 4 channels using TDM in
a 32*4 samples buffer , i will need an other 32*4 samples buffer to do
the de-interleaving since it seems rather complex to do the
de-interleaving inplace. Am i also missing any trick here ?

Thanks,
Laurent Start a New Thread

On Friday 21 July 2006 19:05, Laurent wrote:
> Hello all,
Hi Laurent,
>
> Correct me if i'm wrong, but SPORT's DMA is not able to de-interleave
> samples when we are in TDM mode ( or I2S actually ), since it's not 2D
> capable ?
Using chained DMA might give you a chance to achieve this goal, I guess -
though it might "abuse" some ressources.

> I can't find any trick that would allow me to de-interleave the
> samples while receiving, without using the core, am i missing anything ?
I'm not familiar with this sort of de-interleaving, but did you take into
account, that accessing the DMA buffer from core requires addressing the
buffer.
If the samples would have been de-interleaved already, you would certainly
address them with something like
r0 = dm(i0,m0), where i0 points to the buffer and m0 is 1, so that
auto-addressing points to the always next buffer, while the buffer is set up
as circular buffer (l0, b0 set accordingly).
Addresses would point to DMAbuffer, DMAbuffer+1, DMAbuffer+2, ...

The other approach with the DMA results not de-interleaved would just mean
that you set m0=2 (if you have two channels), which means that
auto-addressing would skip the other channel and point to
DMAbuffer, DMAbuffer+2, DMAbuffer+4, ...

If incoming and outgoing data channels are arranged in a paired manner, you
won't need any de-interleaving.
Works the same for 4 or more channels.

Does this help you?

Bernhard

----
Diese E-Mail enthaelt vertrauliche und/oder rechtlich geschuetzte
Informationen. Wenn Sie nicht der richtige Adressat sind oder diese
E-Mail irrtuemlich erhalten haben, informieren Sie bitte sofort den
Absender und vernichten Sie diese Mail. Das unerlaubte Kopieren sowie
die unbefugte Weitergabe dieser Mail ist nicht gestattet.
Ueber das Internet versandte E-Mails koennen leicht unter fremden Namen
erstellt oder manipuliert werden. Aus diesem Grunde bitten wir um
Verstaendnis, dass wir zu Ihrem und unserem Schutz die rechtliche
Verbindlichkeit der vorstehenden Erklaerungen und Aeusserungen
ausschliessen.

This E-mail may contain confidential and/or privileged information. If
you are not the intended recipient or have received this E-mail in
error, please notify the sender immediately and destroy this E-mail. Any
unauthorized copying, disclosure or distribution of the material in this
E-mail is strictly forbidden.
E-mails via Internet can easily be prepared or manipulated by third
persons. For this reason we trust you will understand that, for your own
and our protection, we rule out the legal validity of the foregoing
statements and comments. Start a New Thread

Hello

I am trying to transfer data from one TS201 processor to other TS201 processor in TS201 EZ Kit. I am using transmit and receive link-port channels for DMA. In EZ-KIT two processors are connected to each other from link port 2. So I use processor 0 DMA channel 6 for transmit, and processor 1 DMA channel 10 for receive purpose. But I could not achieve data transfer between processors. My code look likes as follows:

Exactly the same code is running in both processors except that in processor 0 TRANSMIT_DMA is defined otherwise RECEIVE_DMA is defined (ISRs for linkport2, and DMA channels 10 and 6 exist in the code).

Thanks for your valuable helps....

#include "sysreg.h"
#include "defts201.h"
typedef usigned int INT32U

#define DATA_LEN 256
#define DATA_SIZE 4
INT32U IntRAMData[DATA_LEN];

INT32U xr3_0[4], yr3_0[4];
INT32U dma_control[4]; // link port transmit

#define TRANSMIT_DMA
//#define RECEIVE_DMA
void init_dma()
{

INT32U imaskl, imaskh, i;

#ifdef TRANSMIT_DMA
// Source
dma_control[0] = IntRAMData; // DI reg
dma_control[1] = (DATA_LEN << 16) | DATA_SIZE; // DX reg
dma_control[2] = 0x0; //DY reg
dma_control[3] = TCB_INTMEM | TCB_QUAD | TCB_INT;

// DMA interrupt setup
__builtin_sysreg_write( __UNDER__(IVLINK2) ,(LINK2_ISR));
__builtin_sysreg_write( __UNDER__(IVDMA6) ,(DMA6_ISR));
__builtin_sysreg_write( __UNDER__(IVHW) ,(HWERR_ISR));
imaskl = __builtin_sysreg_read(__UNDER__(IMASKL));
imaskl |= (1< imaskl |= (1< __builtin_sysreg_write(__UNDER__(IMASKL) ,imaskl);

imaskh = __builtin_sysreg_read(__UNDER__(IMASKH));
imaskh |= (1< __builtin_sysreg_write(__UNDER__(IMASKH) ,imaskh);
// enable global interrupt
asm("sqctlst = 0x4;;");
#endif

#ifdef RECEIVE_DMA

// Source
dma_control[0] = IntRAMData; // DI reg
dma_control[1] = (DATA_LEN << 16) | DATA_SIZE; // DX reg
dma_control[2] = 0x0; //DY reg
dma_control[3] = TCB_INTMEM | TCB_QUAD | TCB_INT;
__builtin_sysreg_write( __UNDER__(IVLINK2) ,(LINK2_ISR));
__builtin_sysreg_write( __UNDER__(IVDMA10) ,(DMA10_ISR));
__builtin_sysreg_write( __UNDER__(IVHW) ,(HWERR_ISR));
// DMA interrupt setup
imaskl = __builtin_sysreg_read(__UNDER__(IMASKL));
//imaskl |= (1< imaskl |= (1< __builtin_sysreg_write(__UNDER__(IMASKL) ,imaskl);
imaskh = __builtin_sysreg_read(__UNDER__(IMASKH));
imaskh |= (1< __builtin_sysreg_write(__UNDER__(IMASKH) ,imaskh);
asm("sqctlst = 0x4;;");
#endif
}

void start_dma()
{
INT32U reg32;
asm("xr3:0 = q[j31 + _xr3_0];;");
asm("xr3:0 = q[j31 + _dma_control];;");

#ifdef TRANSMIT_DMA
// enable linkport 2 for trasmit
reg32 = __builtin_sysreg_read(__UNDER__(LTCTL2));
reg32 |= 0x1;
__builtin_sysreg_write(__UNDER__(LTCTL2), reg32);

asm("nop; nop; nop; nop;;");
asm("dc6 = xr3:0;;");
#endif
#ifdef RECEIVE_DMA
asm("dc10 = xr3:0;;");
#endif
//asm("dcs0 = yr3:0;;");

asm("xr3:0 = q[j31 + _xr3_0];;");
asm("yr3:0 = q[j31 + _yr3_0];;");

}

int main()
{

int i;
INT32U *ilathst;
long long dma_stat, reg;

init_dma();
start_dma();

while(1){
dma_stat = __builtin_sysreg_read2(__UNDER__(DSTAT));
#ifdef TRANSMIT_DMA
dma_stat >>= 18;
#endif

#ifdef RECEIVE_DMA
dma_stat >>= 38;
#endif
dma_stat &= 0x7;
if(dma_stat == 0x2){
// tranfer ok
break;
}
}

} Start a New Thread