Sending asyncronous data to SPORT on 21369

Hi all

I am trying now for a few days to send data to the SPORT of a 21369.

I wish to be able to send a number of words, using framed mode with an
externally generated clock and framesync.

I receive data just fine, but for some reason I receive every transmitted
word twice!

A description of my setup:

DSP: 21369 EZ-kit board.
DAI header pin 3 connected to clock output of an FPGA
DAI header pin 5 connected to frame sync output of the FPGA
DAI header pin 7 connected to data out on the FPGA
DAI header pin 25 connected to ground on the FPGA

DAI pin3 via SRU connected to SPORT0_CLK_I
DAI pin5 via SRU connected to SPORT0_FSI
DAI pin7 via SRU connected to SPORT0_DA_I

I have tried the following setups in the DSP:
1. Left justified sample pair with DMA and Chaining (SCHEN_A = 1,
SDEN_A = 1, SLEN = 16, LAFS = 1, FSR = 1, IFS = 0, ICLK = 0, CKRE = 1,
OPMODE = 1, LFS = 0)
2. Left justified sample pair with no DMA (SLEN 16, LAFS = 1, FSR = 1, IFS = 0, ICLK = 0, CKRE = 1, OPMODE = 1, LFS = 0)

The actual code (C code):
// WRPORT(SPCTL0) = (SCHEN_A | SDEN_A | OPMODE |CKRE | SLEN16 | SPEN_A |
LAFS | FSR);
WRPORT(SPCTL0) = ( OPMODE | CKRE | SLEN16 | SPEN_A | LAFS | FSR);

I have also experimented briefly with early framesync, and DSP serial
mode...
Only difference is that when configuring the DSP for non-I2S mode only the
first word (0xAAAA) is received, but this word is still received twice.

The FPGA sends the following:
1. CLK has been configured for continuous, or with 2 clk cycles prior to FS
going high (no difference in result seen from DSP)
2. FS goes high simultaneaous with MSB, and both are valid on the following
rising clock.
3. FS stays high for 16 bits, then goes low.
4. Data transmitted is: 0xAAAA (while FS is high) followed without pause
by: 0x5555

The FPGA is programmed (and this is verified using a scope) to send only
once each time a button on the FPGA board is pressed.

But in the DSP I receive:

0xAAAA
0x5555
0xAAAA
0x5555

i.e. the sequence is received twice.
I hope someone can point out to me what I am doing wrong, because I can't
see why I get this.
And I have been reading the data sheets for 21369, the hardware reference
for 21367-68-69 and EE244 about reprogramming
the SLEN on the first receive interrupt, which is what I was trying to
avoid.

Best regards
Lars Olesen
B,Sc,E,E
DSP SW designer
Bang & Olufsen
Peter Bangs Vej 15
DK-7600 Struer
Denmark

Phone (+45) 96 84 43 59
Fax (+45) 96 84 44 01
e-mail: l...@bang-olufsen.dk Start a New Thread

Hi all
>
>I am trying now for a few days to send data to the SPORT of a 21369.
>
>I wish to be able to send a number of words, using framed mode with an
>externally generated clock and framesync.
>
>I receive data just fine, but for some reason I receive every transmitted
>word twice!
>

Long time ago, I experienced an alike issue.
Reason was simply, that I received one interrupt for RX direction, another for TX.
This was on another processor, however, maybe a 21161.
I don't remember the details, but you might want to check this by temporarily removing all other interrupt except the one of interest, and check again, if you receive double values.

My 2cts, maybe...
Bernhard Start a New Thread