Does anyone know if there are internal pull-up or pull-down resistors on the
programmable flag pins (PF7..PF0) for the 218x series of processors?
If so,
are they configurable? How do I program them?
What state are they (high or low)?
I'm trying write a single software build to run on two different hardware
architectures. Both use an ADSP-2188M. On one architecture, the software is
supposed to change output format modes when the values on PFx flag inputs change
state. No problems with this by itself. On the second architecture, the output
format is not supposed to change, ever, but the PFx flag inputs are floating. I
don't really want to change the circuitry on the second piece of hardware,
but if I know that the PFx flag inputs on the second architecture would stay at
a given value when they are not connected, then I could design the first
hardware architecture and the common software to use whatever the known state of
the 2nd hardware inputs are for this particular output format. I think that
internal pull-ups or pull-down would work well, if they exist in the processor.
internal pull-up on 218x flag inputs?
Started by ●May 11, 2009
Reply by ●May 12, 20092009-05-12
I am almost certain that these pins do not have pullups. They don't on
the 2185M. Check the datasheet to be sure. If they had weak pullups, the
datasheet would indicate this (and the nominal resistance). For example,
the newer SHARCs have 20K pullups.
You can usually add pullups with small networks with the same pitch as
the IC (assuming QFP). I have even used 0201 resistors when I missed a
pullup.
Al Clark
Danville Signal Processing, Inc.
climb2him wrote:
> Does anyone know if there are internal pull-up or pull-down resistors
> on the programmable flag pins (PF7..PF0) for the 218x series of
> processors?
>
> If so,
> are they configurable? How do I program them?
> What state are they (high or low)?
>
> I'm trying write a single software build to run on two different
> hardware architectures. Both use an ADSP-2188M. On one architecture,
> the software is supposed to change output format modes when the values
> on PFx flag inputs change state. No problems with this by itself. On
> the second architecture, the output format is not supposed to change,
> ever, but the PFx flag inputs are floating. I don't really want to
> change the circuitry on the second piece of hardware, but if I know
> that the PFx flag inputs on the second architecture would stay at a
> given value when they are not connected, then I could design the first
> hardware architecture and the common software to use whatever the
> known state of the 2nd hardware inputs are for this particular output
> format. I think that internal pull-ups or pull-down would work well,
> if they exist in the processor.
the 2185M. Check the datasheet to be sure. If they had weak pullups, the
datasheet would indicate this (and the nominal resistance). For example,
the newer SHARCs have 20K pullups.
You can usually add pullups with small networks with the same pitch as
the IC (assuming QFP). I have even used 0201 resistors when I missed a
pullup.
Al Clark
Danville Signal Processing, Inc.
climb2him wrote:
> Does anyone know if there are internal pull-up or pull-down resistors
> on the programmable flag pins (PF7..PF0) for the 218x series of
> processors?
>
> If so,
> are they configurable? How do I program them?
> What state are they (high or low)?
>
> I'm trying write a single software build to run on two different
> hardware architectures. Both use an ADSP-2188M. On one architecture,
> the software is supposed to change output format modes when the values
> on PFx flag inputs change state. No problems with this by itself. On
> the second architecture, the output format is not supposed to change,
> ever, but the PFx flag inputs are floating. I don't really want to
> change the circuitry on the second piece of hardware, but if I know
> that the PFx flag inputs on the second architecture would stay at a
> given value when they are not connected, then I could design the first
> hardware architecture and the common software to use whatever the
> known state of the 2nd hardware inputs are for this particular output
> format. I think that internal pull-ups or pull-down would work well,
> if they exist in the processor.
