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higher clock drawback?

Started by maccordel July 21, 2010
Hi guys,

i am working with real-time implementation of a codec on BF533 eval board. part of my plan to have faster encoder processes before a frame buffering completes, is to make my clock faster.

currently, i am using CCLK'0MHz and SCLKTMHz. I am planning to double the cclk rate. are there any drawbacks in doing this? are there any possibility of hardware destruction (like transistor burning)? i just want to make sure that aside from timing, there will be no other problems in using higher clock rate.

thank you very much for your support.

God bless,

regards,
mac
On Tue, 20 Jul 2010, maccordel wrote:

> Hi guys,
>
> i am working with real-time implementation of a codec on BF533 eval
>board. part of my plan to have faster encoder processes before a frame
>buffering completes, is to make my clock faster.
>
> currently, i am using CCLK'0MHz and SCLKTMHz. I am planning to
>double the cclk rate. are there any drawbacks in doing this? are there
>any possibility of hardware destruction (like transistor burning)? i
>just want to make sure that aside from timing, there will be no other
>problems in using higher clock rate.

Check the manual for that specific part. If the max core clock is 600MHz
you should be fine, but if it is 500MHz then it probably won't work. I
don't think it will hurt the hardware, I think the timing on the latches
won't have enough setup and hold margin and things just won't behave
properly.

Patience, persistence, truth,
Dr. mike