Hi there:
I have a design with ADSP21369 reading data from FIFO connected via EMIF. The
FIFO I am using comes without address bus. The full flag of FIFO is connected to
the IRQ of ADSP to trigger the reading. I am not sure about its memory mapping.
I guess I still need the Msx to select the memory. But how to mapping the memory
if there's no address bus on FIFO and how can I control the data flow? And
to speed up the reading from core, I should use the dma mode, and how can I
configure the start and end address if there is no address bus?
How to read data from FIFO without address bus
Started by ●August 25, 2010
Reply by ●August 25, 20102010-08-25
Hi,
Here's one suggestion .
Use a 2 input OR gate with one of the /MSx lines and /RD line coming in to
generate a /RD_FIFO signal. If you do not use any address lines in
decoding, then the entire address range of MSx will be dedicated to the
FIFO. In this case, it doesn't matter what address you read from in the MSx
address range, as any one will cause a read from the FIFO. With DMA, pick
any address within the range of MSx and then set the Modify to 0 (ie the
address generated by DMA for reading the FIFO should not increment).
Hopefully this makes sense.
Cheers,
George
George Kadziolka
Kaztek Systems
g...@kaztek.com
www.kaztek.com
From: a... [mailto:a...] On Behalf Of
l...@gmail.com
Sent: Wednesday, August 25, 2010 12:21 PM
To: a...
Subject: [adsp] How to read data from FIFO without address bus
Hi there:
I have a design with ADSP21369 reading data from FIFO connected via EMIF.
The FIFO I am using comes without address bus. The full flag of FIFO is
connected to the IRQ of ADSP to trigger the reading. I am not sure about its
memory mapping. I guess I still need the Msx to select the memory. But how
to mapping the memory if there's no address bus on FIFO and how can I
control the data flow? And to speed up the reading from core, I should use
the dma mode, and how can I configure the start and end address if there is
no address bus?
Here's one suggestion .
Use a 2 input OR gate with one of the /MSx lines and /RD line coming in to
generate a /RD_FIFO signal. If you do not use any address lines in
decoding, then the entire address range of MSx will be dedicated to the
FIFO. In this case, it doesn't matter what address you read from in the MSx
address range, as any one will cause a read from the FIFO. With DMA, pick
any address within the range of MSx and then set the Modify to 0 (ie the
address generated by DMA for reading the FIFO should not increment).
Hopefully this makes sense.
Cheers,
George
George Kadziolka
Kaztek Systems
g...@kaztek.com
www.kaztek.com
From: a... [mailto:a...] On Behalf Of
l...@gmail.com
Sent: Wednesday, August 25, 2010 12:21 PM
To: a...
Subject: [adsp] How to read data from FIFO without address bus
Hi there:
I have a design with ADSP21369 reading data from FIFO connected via EMIF.
The FIFO I am using comes without address bus. The full flag of FIFO is
connected to the IRQ of ADSP to trigger the reading. I am not sure about its
memory mapping. I guess I still need the Msx to select the memory. But how
to mapping the memory if there's no address bus on FIFO and how can I
control the data flow? And to speed up the reading from core, I should use
the dma mode, and how can I configure the start and end address if there is
no address bus?
Reply by ●August 25, 20102010-08-25
On Wed, 25 Aug 2010, l...@gmail.com wrote:
> I have a design with ADSP21369 reading data from FIFO connected via
>EMIF. The FIFO I am using comes without address bus. The full flag of
>FIFO is connected to the IRQ of ADSP to trigger the reading. I am not
>sure about its memory mapping. I guess I still need the Msx to select the
>memory. But how to mapping the memory if there's no address bus on FIFO
>and how can I control the data flow? And to speed up the reading from
>core, I should use the dma mode, and how can I configure the start and
>end address if there is no address bus?
That's the whole point of a fifo - it looks like a data stream and not
like memory. there should be an empty flag as well as a full flag, so
you can keep reading the fifo until it is empty.
With the dma, you should be able to set it up to read a single address and
write to an incrementing address. Pick one address for the fifo and
generate a chip select based on that address. When you get a full flag,
the dma can be set to read the whole contents of the fifo in one shot
without monitoring the empty flag. It is just like reading an ADC - there
is one address for source, but you want to fill a buffer with the data.
Patience, persistence, truth,
Dr. mike
> I have a design with ADSP21369 reading data from FIFO connected via
>EMIF. The FIFO I am using comes without address bus. The full flag of
>FIFO is connected to the IRQ of ADSP to trigger the reading. I am not
>sure about its memory mapping. I guess I still need the Msx to select the
>memory. But how to mapping the memory if there's no address bus on FIFO
>and how can I control the data flow? And to speed up the reading from
>core, I should use the dma mode, and how can I configure the start and
>end address if there is no address bus?
That's the whole point of a fifo - it looks like a data stream and not
like memory. there should be an empty flag as well as a full flag, so
you can keep reading the fifo until it is empty.
With the dma, you should be able to set it up to read a single address and
write to an incrementing address. Pick one address for the fifo and
generate a chip select based on that address. When you get a full flag,
the dma can be set to read the whole contents of the fifo in one shot
without monitoring the empty flag. It is just like reading an ADC - there
is one address for source, but you want to fill a buffer with the data.
Patience, persistence, truth,
Dr. mike
Reply by ●August 25, 20102010-08-25
Hi,
Connect one chip select to FIFO read signal and configure asynchronous controller for this chip select. Any reading in the area
configured in memory controller will extract one data from FIFO. You can setup DMA to continously read from one memory location so
you extract all data from FIFO.
Regards
Le 25/08/2010 18:20, l...@gmail.com a rit :
> Hi there:
> I have a design with ADSP21369 reading data from FIFO connected via EMIF. The FIFO I am using comes without address bus. The full flag of FIFO is connected to the IRQ of ADSP to trigger the reading. I am not sure about its memory mapping. I guess I still need the Msx to select the memory. But how to mapping the memory if there's no address bus on FIFO and how can I control the data flow? And to speed up the reading from core, I should use the dma mode, and how can I configure the start and end address if there is no address bus?
>
>
Connect one chip select to FIFO read signal and configure asynchronous controller for this chip select. Any reading in the area
configured in memory controller will extract one data from FIFO. You can setup DMA to continously read from one memory location so
you extract all data from FIFO.
Regards
Le 25/08/2010 18:20, l...@gmail.com a rit :
> Hi there:
> I have a design with ADSP21369 reading data from FIFO connected via EMIF. The FIFO I am using comes without address bus. The full flag of FIFO is connected to the IRQ of ADSP to trigger the reading. I am not sure about its memory mapping. I guess I still need the Msx to select the memory. But how to mapping the memory if there's no address bus on FIFO and how can I control the data flow? And to speed up the reading from core, I should use the dma mode, and how can I configure the start and end address if there is no address bus?
>
>
Reply by ●October 18, 20102010-10-18
I have hooked up my board involving my sampling circuits and FIFO with a
adsp21369 ez-kit evaluation board. The memory selection signal from ADSP
connects to the \RD of FIFO and the \RD from ADSP works as the RCLK of FIFO.
Reading from the HRM of 21369, the momory mapping of AMI:
Table 3-3. AMI Address Memory Map
16-bit (and
PKDIS=0)
External Bank 1 Logical Address: 0x0400_0000 to 0x047F_FFFF Physical Address: 0x0400_0000 to 0x04FF_FFFF
External Bank 2 Logical Address: 0x0800_0000 to 0x087F_FFFF Physical Address: 0x0800_0000 to 0x08FF_FFFF
External Bank 3 Logical Address: 0x0C00_0000 to 0x0C7F_FFFF Physical Address: 0x0C00_0000 to 0x0CFF_FFFF
I am mapping FIFO onto bank 2. I do some hacks for the ldf file:
seg_stak { TYPE(DM RAM) START(0x000bc000) END(0x000bdfff) WIDTH(32) }
seg_heap { TYPE(DM RAM) START(0x000e0000) END(0x000e1fff) WIDTH(32) }
seg_sram { TYPE(DM RAM) START(0x01200000) LENGTH(0x3fff) WIDTH(8) }
seg_sdram { TYPE(PM RAM) START(0x00200000) END(0x0023FFFF) WIDTH(32) }
seg_fifo { TYPE(DMAONLY DM RAM) START(0x08000000) END(0x087FFFFF) WIDTH(16)}
When the FIFO gets full, it triggers the ADSP into IRQ service to read from the FIFO using DMA, I am sure the DMA settings works fine since IIEP ,ICEP , EIEP,, CPEP registers changes accordingly when stepping over the DMA enabling code. But the \MS2 and \RD coming from ADSP don't change at all during the DMA process. Is there anything wroing with the memory mapping? For the register settings side, the MSEN bit is enabled and B2SD is cleared selecting bank2 as non-SDRAM.
Hi there:
>I have a design with ADSP21369 reading data from FIFO connected via EMIF. The FIFO I am using comes without address bus. The full flag of FIFO is connected to the IRQ of ADSP to trigger the reading. I am not sure about its memory mapping. I guess I still need the Msx to select the memory. But how to mapping the memory if there's no address bus on FIFO and how can I control the data flow? And to speed up the reading from core, I should use the dma mode, and how can I configure the start and end address if there is no address bus?
Reading from the HRM of 21369, the momory mapping of AMI:
Table 3-3. AMI Address Memory Map
16-bit (and
PKDIS=0)
External Bank 1 Logical Address: 0x0400_0000 to 0x047F_FFFF Physical Address: 0x0400_0000 to 0x04FF_FFFF
External Bank 2 Logical Address: 0x0800_0000 to 0x087F_FFFF Physical Address: 0x0800_0000 to 0x08FF_FFFF
External Bank 3 Logical Address: 0x0C00_0000 to 0x0C7F_FFFF Physical Address: 0x0C00_0000 to 0x0CFF_FFFF
I am mapping FIFO onto bank 2. I do some hacks for the ldf file:
seg_stak { TYPE(DM RAM) START(0x000bc000) END(0x000bdfff) WIDTH(32) }
seg_heap { TYPE(DM RAM) START(0x000e0000) END(0x000e1fff) WIDTH(32) }
seg_sram { TYPE(DM RAM) START(0x01200000) LENGTH(0x3fff) WIDTH(8) }
seg_sdram { TYPE(PM RAM) START(0x00200000) END(0x0023FFFF) WIDTH(32) }
seg_fifo { TYPE(DMAONLY DM RAM) START(0x08000000) END(0x087FFFFF) WIDTH(16)}
When the FIFO gets full, it triggers the ADSP into IRQ service to read from the FIFO using DMA, I am sure the DMA settings works fine since IIEP ,ICEP , EIEP,, CPEP registers changes accordingly when stepping over the DMA enabling code. But the \MS2 and \RD coming from ADSP don't change at all during the DMA process. Is there anything wroing with the memory mapping? For the register settings side, the MSEN bit is enabled and B2SD is cleared selecting bank2 as non-SDRAM.
Hi there:
>I have a design with ADSP21369 reading data from FIFO connected via EMIF. The FIFO I am using comes without address bus. The full flag of FIFO is connected to the IRQ of ADSP to trigger the reading. I am not sure about its memory mapping. I guess I still need the Msx to select the memory. But how to mapping the memory if there's no address bus on FIFO and how can I control the data flow? And to speed up the reading from core, I should use the dma mode, and how can I configure the start and end address if there is no address bus?
Reply by ●October 18, 20102010-10-18
If RD doesn't change, how do you know there is a DMA process? Is the
correct address going out?
On Sat, 16 Oct 2010, l...@gmail.com wrote:
> I have hooked up my board involving my sampling circuits and FIFO with a adsp21369 ez-kit evaluation board. The memory selection signal from ADSP connects to the \RD of FIFO and the \RD from ADSP works as the RCLK of FIFO.
>
> Reading from the HRM of 21369, the momory mapping of AMI:
>
> Table 3-3. AMI Address Memory Map
> 16-bit (and
> PKDIS=0)
> External Bank 1 Logical Address: 0x0400_0000 to 0x047F_FFFF Physical Address: 0x0400_0000 to 0x04FF_FFFF
> External Bank 2 Logical Address: 0x0800_0000 to 0x087F_FFFF Physical Address: 0x0800_0000 to 0x08FF_FFFF
> External Bank 3 Logical Address: 0x0C00_0000 to 0x0C7F_FFFF Physical Address: 0x0C00_0000 to 0x0CFF_FFFF
>
> I am mapping FIFO onto bank 2. I do some hacks for the ldf file:
>
> seg_stak { TYPE(DM RAM) START(0x000bc000) END(0x000bdfff) WIDTH(32) }
> seg_heap { TYPE(DM RAM) START(0x000e0000) END(0x000e1fff) WIDTH(32) }
> seg_sram { TYPE(DM RAM) START(0x01200000) LENGTH(0x3fff) WIDTH(8) }
> seg_sdram { TYPE(PM RAM) START(0x00200000) END(0x0023FFFF) WIDTH(32) }
> seg_fifo { TYPE(DMAONLY DM RAM) START(0x08000000) END(0x087FFFFF) WIDTH(16)}
>
> When the FIFO gets full, it triggers the ADSP into IRQ service to read from the FIFO using DMA, I am sure the DMA settings works fine since IIEP ,ICEP , EIEP,, CPEP registers changes accordingly when stepping over the DMA enabling code. But the \MS2 and \RD coming from ADSP don't change at all during the DMA process. Is there anything wroing with the memory mapping? For the register settings side, the MSEN bit is enabled and B2SD is cleared selecting bank2 as non-SDRAM.
>
> Hi there:
>> I have a design with ADSP21369 reading data from FIFO connected via EMIF. The FIFO I am using comes without address bus. The full flag of FIFO is connected to the IRQ of ADSP to trigger the reading. I am not sure about its memory mapping. I guess I still need the Msx to select the memory. But how to mapping the memory if there's no address bus on FIFO and how can I control the data flow? And to speed up the reading from core, I should use the dma mode, and how can I configure the start and end address if there is no address bus?
>>
>
correct address going out?
On Sat, 16 Oct 2010, l...@gmail.com wrote:
> I have hooked up my board involving my sampling circuits and FIFO with a adsp21369 ez-kit evaluation board. The memory selection signal from ADSP connects to the \RD of FIFO and the \RD from ADSP works as the RCLK of FIFO.
>
> Reading from the HRM of 21369, the momory mapping of AMI:
>
> Table 3-3. AMI Address Memory Map
> 16-bit (and
> PKDIS=0)
> External Bank 1 Logical Address: 0x0400_0000 to 0x047F_FFFF Physical Address: 0x0400_0000 to 0x04FF_FFFF
> External Bank 2 Logical Address: 0x0800_0000 to 0x087F_FFFF Physical Address: 0x0800_0000 to 0x08FF_FFFF
> External Bank 3 Logical Address: 0x0C00_0000 to 0x0C7F_FFFF Physical Address: 0x0C00_0000 to 0x0CFF_FFFF
>
> I am mapping FIFO onto bank 2. I do some hacks for the ldf file:
>
> seg_stak { TYPE(DM RAM) START(0x000bc000) END(0x000bdfff) WIDTH(32) }
> seg_heap { TYPE(DM RAM) START(0x000e0000) END(0x000e1fff) WIDTH(32) }
> seg_sram { TYPE(DM RAM) START(0x01200000) LENGTH(0x3fff) WIDTH(8) }
> seg_sdram { TYPE(PM RAM) START(0x00200000) END(0x0023FFFF) WIDTH(32) }
> seg_fifo { TYPE(DMAONLY DM RAM) START(0x08000000) END(0x087FFFFF) WIDTH(16)}
>
> When the FIFO gets full, it triggers the ADSP into IRQ service to read from the FIFO using DMA, I am sure the DMA settings works fine since IIEP ,ICEP , EIEP,, CPEP registers changes accordingly when stepping over the DMA enabling code. But the \MS2 and \RD coming from ADSP don't change at all during the DMA process. Is there anything wroing with the memory mapping? For the register settings side, the MSEN bit is enabled and B2SD is cleared selecting bank2 as non-SDRAM.
>
> Hi there:
>> I have a design with ADSP21369 reading data from FIFO connected via EMIF. The FIFO I am using comes without address bus. The full flag of FIFO is connected to the IRQ of ADSP to trigger the reading. I am not sure about its memory mapping. I guess I still need the Msx to select the memory. But how to mapping the memory if there's no address bus on FIFO and how can I control the data flow? And to speed up the reading from core, I should use the dma mode, and how can I configure the start and end address if there is no address bus?
>>
>
