BASIC SHARC HELP.

Hi,
I'm new to DSP programming - though I have experience in assembly programming of micro-controllers.
I have a Analog Devices AD-21479 SHARC EZ-KIT, and I'm trying to program an audio pass-thru using the boards SPDIF In and OUT connectors.
I'm using the on-chip SPDIF receiver to take my incoming SPDIF input stream from the SPDIF input socket, and feeding this on to the SPORT 0 serial in. Similarly, I'm taking the serial output of SPORT 1 and feeding this to the SPDIF transmitter, and on to the SPDIF output socket.
I'm making the required interconnects between two SPORT's and the SPDIF RX and TX sections using the SRU. I'm also configuring the SHARC's PLL and associated clock.
I'm confident that I have set up this correctly because if I temporarily route the SPDIF reciever output directly to the SPDIF transmitter input (again through the SRU), I can pass SPDIF audio streams in, through, and out of the EZ board with no problems.
My problem is that I'm not sure how to configure the interrupts, how to write - and correctly place in program memory - the interrupt service routines for the two SPORT's, and what the correct syntax is for placing the ISR's in the right place in the interrupt vector table.
I'm planning on using the P6I interrupt at vector address 0x44 for the SPORT0 ISR, and the P3I interrupt at 0x38 for the SPORT1 ISR. My problem is that I don't know what the correct asembler systax is, or what section I should place the required code in, to correctly program these ISR's?
Do I need to initialise, or enable, the Interrupt vector table?
In my project, I want to perform sample-by-sample audio processing on the incoming audio stream, triggered by the SPORT0 interrupt. This would would require a jump from SPORT0 ISR vector to the processing code in a separate section of code. Again, I would appreciate any help and advice regarding how to do this - specifically, should this main processing block have it's own section name, and if so, how and where should I place it?
I've attached my code as it stands. When I run it, I can see that the P6I interrupt is being shown as latched in the IMASK LATCH field of the 'Interrupts Registers' window of the debugger interface, and that the P3I 'MASK' and 'MSKP' bits are also set, but I cannot trap any activity in either of the two ISR sections at the end of my code, and don't get the jumps to the ISR vector locations.
Like I said. I'm new to DSP and SHARC, and I'm sure I'm blind to a simple and trivial mistake. I would be much obliged if someone could copy my code, edit in the required corrections to the ISR's and associated set-up, and re-post it.
Thanks for your time.
Paul.
//*********************************************************************
//
// TITLE:- SPDIF AUDIO FRAMEWORK FOR AD 21479 EZ-KIT.
// DATE:- 04.05.2011
// BY:- P.S.
// FILE:- frame.asm
//
// NOTE:- J6 (SPDIF OUT) ON EZ BOARD CONNECTS TO DPI_P1 (PIN 1)
// NOTE:- J7 (SPDIF IN) ON EZ BOARD CONNECTS TO DPI_P18 (PIN 18)
//*********************************************************************

#include
#include
#define SRUDEBUG

.SECTION/PM seg_pmco;

.GLOBAL _main;
_main:

//SET UP PLL AND WAIT FOR STABILISATION

r0 = 0x00020120;
r0 = bset r0 by INDIV;
r0 = bset r0 by DIVEN;
dm(PMCTL) = r0;
r0 = bset r0 by PLLBP;
r0 = bclr r0 by DIVEN;
dm(PMCTL) = r0;
lcntr@96;
do PLL_LOCK until lce;
nop;
PLL_LOCK:
r0 = dm(PMCTL);
r0 = bclr r0 by PLLBP;
dm(PMCTL) = r0;
lcntr@96;
do PLL_STAB until lce;
nop;
PLL_STAB: nop;

// ENABLE SDRAM MEMORY
r0 = 0x00100004;
dm(SYSCTL) = r0;
r0 = 0x000000F1;
dm(EPCTL) = r0;
r0 = 0x2B051363;
dm(SDCTL) = r0;
r0 = 0x00030406;
dm(SDRRC) = r0;
r0 = 0x00100004;
dm(SYSCTL) = r0;
r0 = 0x000007C1;
dm(AMICTL1) = r0;
r0 = 0x00000083;
dm(AMICTL3) = r0;

//NOTE:- USING SPORT 0 FOR SPDIF RX & SPORT 1 FOR SPDIF TX.

//SPORT 0 & 1 RESETS.
r0 = 0;
dm(SPMCTL0) = r0;
dm(SPCTL0) = r0;
dm(DIV0) = r0;
dm(SPMCTL1) = r0;
dm(SPCTL1) = r0;

//SPDIF TX AND RX SET-UP.
r0 = 0;
dm(DIRCTL) = r0;
r0 = 0x00000241;
dm(DITCTL) = r0;

//SPORT 0 RX SET-UP.
r0 = 0xE00109F1;
dm(SPCTL0) = r0;

//SPORT 1 TX SET-UP.
r0 = 0x220109F1;
dm(SPCTL1) = r0;

//TIE ALL SRU PIN BUFFER INPUTS LOW
// (DAI_PBxx_I) GROUP D.
SRU(LOW, DAI_PB01_I);
SRU(LOW, DAI_PB02_I);
SRU(LOW, DAI_PB03_I);
SRU(LOW, DAI_PB04_I);
SRU(LOW, DAI_PB05_I);
SRU(LOW, DAI_PB06_I);
SRU(LOW, DAI_PB07_I);
SRU(LOW, DAI_PB08_I);
SRU(LOW, DAI_PB09_I);
SRU(LOW, DAI_PB10_I);
SRU(LOW, DAI_PB11_I);
SRU(LOW, DAI_PB12_I);
SRU(LOW, DAI_PB13_I);
SRU(LOW, DAI_PB14_I);
SRU(LOW, DAI_PB15_I);
SRU(LOW, DAI_PB16_I);
SRU(LOW, DAI_PB17_I);
SRU(LOW, DAI_PB18_I);
SRU(LOW, DAI_PB19_I);
SRU(LOW, DAI_PB20_I);

//TIE ALL PIN BUFFER ENABLE INPUTS LOW
//(DAI_PBENxx_I) GROUP F.
SRU(LOW, PBEN01_I);
SRU(LOW, PBEN02_I);
SRU(LOW, PBEN03_I);
SRU(LOW, PBEN04_I);
SRU(LOW, PBEN05_I);
SRU(LOW, PBEN06_I);
SRU(LOW, PBEN07_I);
SRU(LOW, PBEN08_I);
SRU(LOW, PBEN09_I);
SRU(LOW, PBEN10_I);
SRU(LOW, PBEN11_I);
SRU(LOW, PBEN12_I);
SRU(LOW, PBEN13_I);
SRU(LOW, PBEN14_I);
SRU(LOW, PBEN15_I);
SRU(LOW, PBEN16_I);
SRU(LOW, PBEN17_I);
SRU(LOW, PBEN18_I);
SRU(LOW, PBEN19_I);
SRU(LOW, PBEN20_I);
//************************************************************************************
//CONNECT SPDIF INPUT TO DAI PIN 18 (J7 SPDIF IN)
//pin buffer input LOW.
//Tie the pin buffer enable input LOW.
//Connect the SPDIF Receiver input to DAI pin 18 (J7 - SPDIF IN).
SRU(LOW,DAI_PB18_I);
SRU(LOW,PBEN18_I);
SRU(DAI_PB18_O,DIR_I);
//************************************************************************************
//CONNECT SPDIF OUTPUT TO DAI PIN 18 (J6 SPDIF OUT)
//Enable pin buffer
//Connect the SPDIF transmitter output to DAI pin 1
//(J6 - SPDIF OUT).
SRU (HIGH, PBEN01_I);
SRU (DIT_O, DAI_PB01_I);
//************************************************************************************
//CONNECT SPDIF RX HF CLOCK, CLOCK AND FRAME SYNC TO TX HF CLOCK, CLOCK AND FRAME SYNC.
//Connect HF SPDIF clock from SPDIF reciever to SPDIF transmitter.
//Clock from SPDIF clock from reciever to SPDIF transmitter.
//Connect frame sync from SPDIF reciever to SPDIF transmitter.
SRU(DIR_TDMCLK_O, DIT_HFCLK_I);
SRU(DIR_CLK_O, DIT_CLK_I);
SRU(DIR_FS_O, DIT_FS_I);
//************************************************************************************
//CONNECT SPDIF DIR CLOCK, FRAME SYNC AND DATA TO SPORT 0 - SPORT 0 IS RECIEVER SPORT
//Connect clock from SPDIF RX to Sport 0 clock in
//Connect Frame sync from SPDIF RX to Sport 0
//Data from SPDIF RX to Sport 0 data in
SRU(DIR_CLK_O,SPORT0_CLK_I);
SRU(DIR_FS_O,SPORT0_FS_I);
SRU(DIR_DAT_O,SPORT0_DA_I);
//************************************************************************************
//CONNECT SPDIF DIR CLOCK AND FRAME SYNC TO SPORT 1 - SPORT 1 IS TRANSMITTER SPORT
//Connect clock from SPDIF RX to Sport 0 clock in
//Connect Frame sync from SPDIF RX to Sport 0
SRU(DIR_CLK_O,SPORT1_CLK_I);
SRU(DIR_FS_O,SPORT1_FS_I);
//************************************************************************************
//!!!!! FOR FIRST TESTING - CONNECT SPORT0 (RX) DATA OUTPUT TO SPORT1 DATA INPUT !!!!!
SRU(SPORT0_DA_O,SPORT1_DA_I); // RX Data Sport0 to TX Dat in SPORT1
//************************************************************************************
//CONNECT SPORT1 OUTPUT TO SPDIF TX INPUT
//Output Sport1 to DIT Data input
//Output DIR Data to DIT Data input!COMMENT THIS TO TEST SPORT 0 ISR!
//!UNCOMMENT NEXT LINE TO TEST SPORT 1 ISR!
SRU(SPORT1_DA_O,DIT_DAT_I);
//!COMMENT NEXT LINE TO TEST SPORT 1 ISR!
// SRU(DIR_DAT_O,DIT_DAT_I);
//************************************************************************************
//SPORT's 0 & 1 INTERRUPT ENABLE
//SET-UP ENDLESS LOOP AND WAIT TO PROCESS RECEIVED AUDIO DATA.
bit set IMASK P3I;
bit set IMASK P6I;
//GLOBALLY ENABLE INTERUPTS
bit set MODE1 IRPTEN;

do ENDLESS until forever;
ENDLESS: nop;

._main.END: Start a New Thread

Howdy Paul,

On Sat, 14 May 2011, p...@btinternet.com wrote:

> I'm planning on using the P6I interrupt at vector address 0x44 for the
>SPORT0 ISR, and the P3I interrupt at 0x38 for the SPORT1 ISR. My problem
>is that I don't know what the correct asembler systax is, or what section
>I should place the required code in, to correctly program these ISR's?
> Do I need to initialise, or enable, the Interrupt vector table?

Yes. The vector table should be one of the files in the pass through
code example. You modify it with jumps to your isr's and by delcaring
the address as extern in the vector table file and global in the main
file. The linker then does the rest. When an interrupt happens, you'll
have the right jump code in the right place and it will work.

Patience, persistence, truth,
Dr. mike Start a New Thread