I'm using three Sharc 21060, for the comunication between them i'm using dma's
on the linkports. Here is my question, if lstat=3 on one of the linkports (=the
incomming buffer is full), what happens then? is the buffer cleared the next
time I want to use the linkport? or is the first data I get the data in the
buffer? do I need to clear it myself?
I know that the transfer that made the buffer full is lost, I know how to handle
that, that is not the question. And I know why it got full, the dma was not
ready to receive yet anyone who knows anything about this please answer, I can't find this
information in the manual
On Wed, 29 Dec 1999, Per Karlstrand (EMW) wrote:|
> I'm using three Sharc 21060, for the comunication between them i'm
> using dma's on the linkports. Here is my question, if lstat=3 on one of
> the linkports (=the incomming buffer is full), what happens then?
nothing. the transmitting link port stops because the hardware handshaking
of the link ports signals a full receive buffer to the transmitter.
> is the buffer cleared the next time I want to use the linkport?
if 'use' means read from the link buffer, then the buffer will be emptied,
LxSTAT changes to 2. if you read another word, LxSTAT chages to 0 and now
the corresponding link buffer is empty. any further reads will cause a
hang (a dma simply stops).
however, if the transmitting side continues to write, then the link buffer
won't get empty. it will immediately be filled up again (until LxSTAT=3).
if 'use' means resetting and re-enabling the link buffer by clearing the
corresponding LCTL bit (LxEN) and setting it up again: the buffer is
> or is the first data I get the data in the buffer?
yes. it is a true fifo (in my experience).
> do I need to clear it myself?
the buffer is only cleared when you reset the corresonding link buffer
(setting the LxEN bit to zero)
if you read all words from the buffer and no new data words are received. > anyone who knows anything about this please answer, I can't find this
information in the manual
hope i could help.
Dear SHARC specialists,|
recently I watched the Bus Request Lines of four SHARCs 21062 on a
Transtech ASP P15. What I finally found on my Logic Analyser is quite
confusing to me: SHARC No. 1,2 and 3 behave as described in the manual.
I see the arbitration and every "lower" priorized SHARC deasserts it's
busrequest signal. The "master" sharc with No. 0 always has a zero on it's
BR0 line. As I far as I understand the manual and timing diagrams, the highest
priorized DSP (i.e. Sharc 0) wins therefore the busmastership ?!
Just to make sure, that no other DSP is granted the bus I wrote a little
which lets communicate two lower priorized SHARCs via broadcast and direct-
slave write. Amazingly the communication takes place, so the lower priorized
DSP access the external system bus.
I am very happy, the bus access takes place, but I really would like to know
what is going on. Did I miss something ? Is it normal in a four-processor
environment that Sharc 0 always asserts BR0 ?
Any answer is highly appreciated
thanks in advance
Technische Informatik I
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