Hello,
I am working on TMS320F2808 DSP controllor Starter kit from Spectrum Digital. I
am working on the SPI peripheral. I have configured DSP starter kit as SPI slave
and Another master keeps sending some standard data pattern to slave and slave
too sends particular data pattern to Master. I wouldlike to know weather the SPI
line SPISTE is it Edge triggered or Level triggered. Suppose Master is sending 5
bytes of data to slave in a One cycle, so Master initiates the Cycle by
lowereing SPISTE line and by clocking the SPICLK line. By any chance during the
Data cycle Slave is not ready,ie. in Slave SPI peripheral is in reset state; And
the slave gets ready during mid of the Cycle say after master has clocked 2
bytes. Since SPISTE will be low in entire cycle, so will slave receive remaining
3 bytes of total 5 bytes? or it waits for SPISTE to be edge trigerred then only
it starts receiving the bytes?
Also i am using debugger and putting breakpoints in the code, will this effect
the working of 2808 as SPI slave. What should be the value of SPIPRI register
value while using debugger and without debugger in DSP controller as SPI Slave.
Please come back to me if you need more inputs.
Thank you
Harish
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