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FIR on C33 DSK Help

Started by josemvarona March 30, 2005


Hello.

I purchased the C33 DSK for a Real-time DSP course, and modified some
code found in this post, and using the PCM3003.asm provided with the
kit, to develop a low pass FIR filter. Now, when I run the code I get
a garbled signal along all frequency ranges. I tested the Fs(LRCIN)
with an oscilloscope to determine whether it was correct, and found it
to be at 36.3kHz.

Any help would be appreciated.

Jose

CODE BELOW-------------------------

;------------------------------
;LB1.ASM
;Loopback test for VC33 DSK & PM3003
;March 2005 - Real Time DSP Course
;------------------------------
DMA_ctrl .set 0808000h ; DMA cntl
DMA_srce .set 0808004h ; DMA srce address
DMA_dest .set 0808006h ; DMA dest address
DMA_xfr .set 0808008h ; DMA xfer counter
T0_ctrl .set 0808020h ; TIM0 gl control
T0_count .set 0808024h ; TIM0 count
T0_prd .set 0808028h ; TIM0 prd
T1_ctrl .set 0808030h ; TIM1 gl control
T1_count .set 0808034h ; TIM1 count
T1_prd .set 0808038h ; TIM1 prd
S0_gctrl .set 0808040h ; SP 0 global control
S0_xctrl .set 0808042h ; SP 0 FSX/DX/CLKX port ctl
S0_rctrl .set 0808043h ; SP 0 FSR/DR/CLKR port ctl
S0_tctrl .set 0808044h ; SP 0 R/X timer control
S0_tcount .set 0808045h ; SP 0 R/X timer counter
S0_tprd .set 0808046h ; SP 0 R/X timer period
S0_xdata .set 0808048h ; SP 0 Data transmit
S0_rdata .set 080804Ch ; SP 0 Data receive
S1_gctrl .set 0808050h ; SP 1 global control
S1_xctrl .set 0808052h ; SP 1 FSX/DX/CLKX port ctl
S1_rctrl .set 0808053h ; SP 1 FSR/DR/CLKR port ctl
S1_tctrl .set 0808054h ; SP 1 R/X timer control
S1_tcount .set 0808055h ; SP 1 R/X timer counter
S1_tprd .set 0808056h ; SP 1 R/X timer period
S1_xdata .set 0808058h ; SP 1 Data transmit
S1_rdata .set 080805Ch ; SP 1 Data receive
e_buscon .set 0808060h ; Exp bus control
p_buscon .set 0808064h ; Pri bus control

;
; Kernel functions can be accessed through the function
; jump table which holds the address of each function
;
JJUMP .set 0809ff4H ;<- Base address
JXWRIT .set 0809ff5H ;
JXREAD .set 0809ff6H ;
JXCTXT .set 0809ff7H ;
JXRUNF .set 0809ff8H ;
JXSTEP .set 0809ff9H ;
JXHALT .set 0809ffAH ;
JW_HOST .set 0809ffBH ;
JR_HOST .set 0809ffCH ;
JSPARE .set 0809ffdH ;

RAM0 .set 0x809802
RAM1 .set 0x809c00
RAM2 .set 0x800000
RAM3 .set 0x804000
XINT0_ADDR .set 0x809FC5

.start "CODEC",RAM0 ; start assembling in RAM Block 0
.start "int_vects",XINT0_ADDR ; here's where the XINT0 vector is
.start ".data",RAM1 ; RAM1 data section

.data ; on starting program go
to this point
COEFF .float
-4.6726126e-004,-2.6059912e-004,3.4595091e-019,3.3818036e-004,
.float
7.6774639e-004,1.2797449e-003,1.8322331e-003,2.3456206e-003,
.float
2.7057687e-003,2.7758505e-003,2.4164857e-003,1.5120926e-003,
.float
-1.4173343e-018,-2.1021191e-003,-4.6752962e-003,-7.4892424e-003,
.float
-1.0206602e-002,-1.2403119e-002,-1.3603220e-002,-1.3328244e-002,
.float
-1.1152504e-002,-6.7607717e-003,3.0980336e-018,9.0817756e-003,
.float
2.0215337e-002,3.2912995e-002,4.6495534e-002,6.0141882e-002,
.float
7.2957138e-002,8.4052158e-002,9.2626248e-002,9.8043860e-002,
.float
9.9896656e-002,9.8043860e-002,9.2626248e-002,8.4052158e-002,
.float
7.2957138e-002,6.0141882e-002,4.6495534e-002,3.2912995e-002,
.float
2.0215337e-002,9.0817756e-003,3.0980336e-018,-6.7607717e-003,
.float
-1.1152504e-002,-1.3328244e-002,-1.3603220e-002,-1.2403119e-002,
.float
-1.0206602e-002,-7.4892424e-003,-4.6752962e-003,-2.1021191e-003,
.float
-1.4173343e-018,1.5120926e-003,2.4164857e-003,2.7758505e-003,
.float
2.7057687e-003,2.3456206e-003,1.8322331e-003,1.2797449e-003,
.float
7.6774639e-004,3.3818036e-004,3.4595091e-019,-2.6059912e-004,
H0 .float -4.6726126e-004
LENGTH .set 65
CO_ADDR .word H0
.brstart "IN_L_BUFF",128
IN_L .sect "IN_L_BUFF"
.loop LENGTH
.float 0.0
.endloop
.brstart "IN_R_BUFF",128
IN_R .sect "IN_R_BUFF"
.loop LENGTH
.float 0
.endloop
IN_L_ADDR .word IN_L
IN_R_ADDR .word IN_R
LRCIN .word 0x80A000 ; LRCIN is bit 4 of this location
INSAMPLE_R .word 0 ;
INSAMPLE_L .word 0 ;
OUTSAMPLE_R .word 0 ;
OUTSAMPLE_L .word 0 ;
GIE .set 0x2000 ; This bit in ST turns on
interrupt .sect "CODEC" ;
.entry PROG_INIT ;
PROG_INIT ldp T0_ctrl ;
ldi @stack,SP ; setup the stack
call AICINIT ; sets up the DSK.
ldi 0x34,IE ; Enable the XINT RINT INT2
ldi LENGTH,BK
ldi @IN_L_ADDR,AR2
ldi @IN_R_ADDR,AR3

; THE TIMER AND SERIAL PORT
ARE NOW BOTH RUNNING - ENABLE INTTERUPT.
main
or GIE,ST ; Turn on INTS
idle ; wait for interrupt
andn GIE,ST ; Turn off INTS
br main ; pointless endless loop. ;-------------------------------
; XINT0 Interrupt Service Routine
;----------------------------------
XINT0 push ST ; Interrupt service routine
push R0 ; save fp significance
pushf R0 ;
push AR1 ;
ldi @LRCIN,AR1 ;
ldi *AR1,R0 ;
and 0x10,R0 ; this isolates the LRCIN bit
bnz Lft ;
Rght ldi @OUTSAMPLE_R,R0 ;
br Shift ;
Lft ldi @OUTSAMPLE_L,R0 ;
Shift
lsh -12,R0 ;
sti R0,@S0_xdata ;
ldi 0,R5
sti R5,@INSAMPLE_L
sti R5,@INSAMPLE_R
sti R5,@OUTSAMPLE_L
sti R5,@OUTSAMPLE_R
pop AR1 ;
popf R0 ;
pop R0 ; restore significance
pop ST ;
reti ;

;-----------------------------
; RINT0 Interrupt Service Routine
;
RINT0 push ST ; Interrupt service routine
push R0 ; save fp significance
pushf R0 ;
push AR1 ;
ldi @LRCIN,AR1 ;
ldi *AR1,R0 ; Sample the LRCIN bit, and
then store the data in the right place
and 0x10,R0 ; isolated the LRCIN bit
bnz left ;
right ldi @S0_rdata,R0 ;
sti R0,@INSAMPLE_R ;
br fin_int ;
left ldi @S0_rdata,R0 ;
sti R0,@INSAMPLE_L ;
fin_int
CALL INT_SER_L ;
CALL INT_SER_R ;
pop AR1 ;
popf R0 ;
pop R0 ; restore significance
pop ST ;
reti ;
;----FIR ALgorithm Left Side-----------------------
INT_SER_L ldi @INSAMPLE_L,R0

float R0,R4
stf R4,*AR2++%
ldi @CO_ADDR,R2
ldf 0.0,R0
ldf 0.0,R3
RPTS LENGTH - 1
mpyf3 *R2--,*AR2++%,R0
|| ADDF3 R0,R3,R3
ADDF3 R0,R3,R3
fix R3,R3
sti R3,@OUTSAMPLE_L

rets
;----FIR Algorithm Left Side----------------------
INT_SER_R

ldi @INSAMPLE_R,R0
float R0,R4
stf R4,*AR3++%
ldi @CO_ADDR,R2
ldf 0.0,R0
ldf 0.0,R3
RPTS LENGTH - 1
mpyf3 *R2--,*AR3++%,R0
|| ADDF3 R0,R3,R3
ADDF3 R0,R3,R3
fix R3,R3
sti R3,@OUTSAMPLE_R

rets

;---------------------------
; CODE TO INITIALISE THE TIMER AND SERIAL PORTS.
;-----------
; params for aic PCM3003 initialization ;
;---------
TIM0_PRD .word 4 ; (Fsys/2)/TIM0_PRD=TCKL0 (Fs =TCKL0/256)
S0_gctrl_val .word 0x0E970300 ; Serial port control register
values
S0_xctrl_val .word 0x00000111 ;
S0_rctrl_val .word 0x00000111 ;
;--------------------------------
XCLKSRCE .set 0 << 6 ; 0=external 1= internal
RCLKSRCE .set 0 << 7 ;
XVAREN .set 0 << 8 ; VAREN 0 1
RVAREN .set 0 << 9 ; FS ____---------_____
XFSM .set 0 <<10 ; 0=burst 1=continuous
RFSM .set 0 <<11 ;
CLKXP .set 1 <<12 ;
CLKRP .set 1 <<13 ;
DXP .set 0 <<14 ;
DRP .set 0 <<15 ;
FSXP .set 1 <<16 ;
FSRP .set 1 <<17 ;
XLEN .set 11b<<18 ; 00=8 01 10$ 112
RLEN .set 11b<<20 ;
EXTINT .set 0 <<22 ;
EXINT .set 1 <<23 ;
ERTINT .set 0 <<24 ;
ERINT .set 1 <<25 ;
S0 .sdef XCLKSRCE|RCLKSRCE|XVAREN|RVAREN|XFSM|RFSM|CLKXP|CLKRP ;
S0 .sdef S0|DXP|DRP|FSXP|FSRP|EXTINT|EXINT|ERTINT|ERINT ;
SPBITS .set 32 ;
BITSEL .set ((SPBITS/8)-1) // 0=8, 1, 2$ and 32 bits ;
S0 .sdef S0|(BITSEL<<18)|(BITSEL<<20) ;
S0gctrl_rst .word S0 ;
S0gctrl_run .word S0|0x0C000000 ;
S0xctrl .set 0x00000111 ;
S0rctrl .set 0x00000111 ;
S0cpld .word 0x80A000 ; CPLD status byte contains LRCIN

;------------
; initializes the serial port, codec and timers
; JP4
; Pins 1-2 16bit open; 32bit short
; Pins 3-4 DEM1 short to pullup (Deemphasis 1)
; Pins 5-6 DEM0 short to pullup (Deemphasis 0)
; JP1
; Pins 1-2 short to AVDD Mic channel 1
; Pins 3-4 short to AVDD Mic channel 2
;---------------
_SQRMODE .word 0x0 ;0x10
AICINIT ldi 0,R0 ; halt the timer
sti R0,@T0_ctrl ;
ldi @TIM0_PRD,R0 ; put a count in prd
sti R0,@T0_prd ;
ldi 0x283,R0 ; set bits to start timer
or @_SQRMODE,R0
sti R0,@T0_ctrl ; timer is now running!
ldi 0,R0 ;
sti R0,@T0_count ; T0_count = 0
;------------------------------
ldi S0xctrl,R0 ; Init xmit/recv pin control
sti R0,@S0_xctrl ; S0_xctrl = S0xctrl
; transmit control
ldi S0rctrl,R0 ;
sti R0,@S0_rctrl ; S0_rctrl = S0rctrl
; receive control
ldi @S0gctrl_rst,R0 ; Reset serial port
sti R0,@S0_gctrl ; S0_gctrl = S0gctrl_rst
ldi @S0gctrl_run,R0 ; Run serial port
sti R0,@S0_gctrl ; S0_gctrl = S0gctrl_run
ldi 0,R0 ;
sti R0,@S0_xdata ;
sti R0,@S0_rdata ;
sti R0,@INSAMPLE_L ;
sti R0,@INSAMPLE_R ;
STI R0,@OUTSAMPLE_L ;
STI R0,@OUTSAMPLE_R ;
rets ; return from subroutine

;-------------
; STACK
;------------
stack .word $+1 ; the word at stack is the
address of the next cell
; Now install the interrupt vector

.sect "int_vects" ; name the section something
br XINT0 ;
br RINT0 ;
.end
trl = S0gctrl_rst
ldi @S0gctrl_run,R0 ; Run serial port
sti R0,@S0_gctrl ; S0_gctrl = S0gctrl_run
ldi 0,R0 ;
sti R0,@S0_xdata ;
sti R0,@S0_rdata ;
sti R0,@INSAMPLE_L ;
sti R0,@INSAMPLE_R ;
STI R0,@OUTSAMPLE_L ;
STI R0,@OUTSAMPLE_R ;
rets ; return from subroutine

;-------------
; STACK
;------------
stack .word $+1 ; the word at stack is the
address of the next cell
; Now install the interrupt vector

.sect "int_vects" ; name the section something
br XINT0 ;
br RINT0 ;
.end


Hello Jose

The timer period register is set to 4, yielding a 9.375 MHz master clock (MCLK) to the PCM3003.  This is then divided by 256 to create the LRCIN (Left/Right clkin).  You need to pick a different divisor for 48Khz operation. But then, this might not be the problem.

Go back and have another look at the C and ASM examples that come with the board.  The C example might be easier to follow and has code within it that calculates FIR coefficients before running them.  The filter definitions and resulting coefficients are pretty much  limited to band pass/reject, but it works.  Cut out the coefficient generator and you would have working code.

The next step is to look carefully at how the compiler version of an FIR differs from a hand optimized ASM routine. The DSP has on-chip hardware to speed things up... but the data and code limitations of C dont always work well with hardware.  This is where you should be learning about mixing C/ASM.

Best regards
Keith Larson

josemvarona wrote:


Hello.

I purchased the C33 DSK for a Real-time DSP course, and modified some
code found in this post, and using the PCM3003.asm provided with the
kit, to develop a low pass FIR filter. Now, when I run the code I get
a garbled signal along all frequency ranges. I tested the Fs(LRCIN)
with an oscilloscope to determine whether it was correct, and found it
to be at 36.3kHz.

Any help would be appreciated.

Jose

CODE BELOW-------------------------

;------------------------------
;LB1.ASM
;Loopback test for VC33 DSK & PM3003
;March 2005 - Real Time DSP Course
;------------------------------
DMA_ctrl  .set 0808000h  ;  DMA cntl
DMA_srce  .set 0808004h  ;  DMA srce address
DMA_dest  .set 0808006h  ;  DMA dest address
DMA_xfr   .set 0808008h  ;  DMA xfer counter
T0_ctrl   .set 0808020h  ;  TIM0 gl control
T0_count  .set 0808024h  ;  TIM0 count
T0_prd    .set 0808028h  ;  TIM0 prd
T1_ctrl   .set 0808030h  ;  TIM1 gl control
T1_count  .set 0808034h  ;  TIM1 count
T1_prd    .set 0808038h  ;  TIM1 prd
S0_gctrl  .set 0808040h  ;  SP 0 global control
S0_xctrl  .set 0808042h  ;  SP 0 FSX/DX/CLKX port ctl
S0_rctrl  .set 0808043h  ;  SP 0 FSR/DR/CLKR port ctl
S0_tctrl  .set 0808044h  ;  SP 0 R/X timer control
S0_tcount .set 0808045h  ;  SP 0 R/X timer counter
S0_tprd   .set 0808046h  ;  SP 0 R/X timer period
S0_xdata  .set 0808048h  ;  SP 0 Data transmit
S0_rdata  .set 080804Ch  ;  SP 0 Data receive
S1_gctrl  .set 0808050h  ;  SP 1 global control
S1_xctrl  .set 0808052h  ;  SP 1 FSX/DX/CLKX port ctl
S1_rctrl  .set 0808053h  ;  SP 1 FSR/DR/CLKR port ctl
S1_tctrl  .set 0808054h  ;  SP 1 R/X timer control
S1_tcount .set 0808055h  ;  SP 1 R/X timer counter
S1_tprd   .set 0808056h  ;  SP 1 R/X timer period
S1_xdata  .set 0808058h  ;  SP 1 Data transmit
S1_rdata  .set 080805Ch  ;  SP 1 Data receive
e_buscon  .set 0808060h  ;  Exp bus control
p_buscon  .set 0808064h  ;  Pri bus control

;
; Kernel functions can be accessed through the function
; jump table which holds the address of each function
;
JJUMP    .set    0809ff4H    ;<- Base address
JXWRIT   .set    0809ff5H    ;
JXREAD   .set    0809ff6H    ;
JXCTXT   .set    0809ff7H    ;
JXRUNF   .set    0809ff8H    ;
JXSTEP   .set    0809ff9H    ;
JXHALT   .set    0809ffAH    ;
JW_HOST  .set    0809ffBH    ;
JR_HOST  .set    0809ffCH    ;
JSPARE   .set    0809ffdH    ;

RAM0    .set    0x809802
RAM1    .set    0x809c00
RAM2    .set    0x800000
RAM3    .set    0x804000
XINT0_ADDR .set 0x809FC5

        .start "CODEC",RAM0             ; start assembling in RAM Block 0
        .start "int_vects",XINT0_ADDR   ; here's where the XINT0 vector is
        .start ".data",RAM1             ; RAM1 data section

        .data                               ; on starting program go
to this point
COEFF   .float
-4.6726126e-004,-2.6059912e-004,3.4595091e-019,3.3818036e-004,
        .float
7.6774639e-004,1.2797449e-003,1.8322331e-003,2.3456206e-003,
        .float
2.7057687e-003,2.7758505e-003,2.4164857e-003,1.5120926e-003,
        .float
-1.4173343e-018,-2.1021191e-003,-4.6752962e-003,-7.4892424e-003,
        .float
-1.0206602e-002,-1.2403119e-002,-1.3603220e-002,-1.3328244e-002,
        .float
-1.1152504e-002,-6.7607717e-003,3.0980336e-018,9.0817756e-003,
        .float
2.0215337e-002,3.2912995e-002,4.6495534e-002,6.0141882e-002,
        .float
7.2957138e-002,8.4052158e-002,9.2626248e-002,9.8043860e-002,
        .float
9.9896656e-002,9.8043860e-002,9.2626248e-002,8.4052158e-002,
        .float
7.2957138e-002,6.0141882e-002,4.6495534e-002,3.2912995e-002,
        .float
2.0215337e-002,9.0817756e-003,3.0980336e-018,-6.7607717e-003,
        .float
-1.1152504e-002,-1.3328244e-002,-1.3603220e-002,-1.2403119e-002,
        .float
-1.0206602e-002,-7.4892424e-003,-4.6752962e-003,-2.1021191e-003,
        .float
-1.4173343e-018,1.5120926e-003,2.4164857e-003,2.7758505e-003,
        .float
2.7057687e-003,2.3456206e-003,1.8322331e-003,1.2797449e-003,
        .float
7.6774639e-004,3.3818036e-004,3.4595091e-019,-2.6059912e-004,
H0      .float -4.6726126e-004
LENGTH  .set 65
CO_ADDR .word H0
        .brstart "IN_L_BUFF",128
IN_L    .sect "IN_L_BUFF"
        .loop LENGTH
        .float 0.0
        .endloop
        .brstart "IN_R_BUFF",128
IN_R    .sect "IN_R_BUFF"
        .loop LENGTH
        .float 0
        .endloop
IN_L_ADDR .word IN_L
IN_R_ADDR .word IN_R
LRCIN   .word 0x80A000                  ; LRCIN is bit 4 of this location
INSAMPLE_R   .word 0                    ;
INSAMPLE_L   .word 0                    ;
OUTSAMPLE_R     .word 0               ;
OUTSAMPLE_L     .word 0               ;
GIE     .set 0x2000                     ; This bit in ST turns on
interrupt         .sect  "CODEC"                  ;
        .entry PROG_INIT                ;
PROG_INIT       ldp T0_ctrl             ;
                ldi @stack,SP           ; setup the stack
                call AICINIT            ; sets up the DSK.
                ldi 0x34,IE              ; Enable the XINT RINT INT2
                ldi LENGTH,BK
                ldi @IN_L_ADDR,AR2
                ldi @IN_R_ADDR,AR3

                                        ; THE TIMER AND SERIAL PORT
ARE NOW BOTH RUNNING - ENABLE INTTERUPT.
main
        or GIE,ST                       ; Turn on INTS
        idle                            ; wait for interrupt
        andn GIE,ST                     ; Turn off INTS
        br main                         ; pointless endless loop. ;-------------------------------
; XINT0 Interrupt Service Routine
;----------------------------------
XINT0   push ST                         ; Interrupt service routine
        push R0                         ; save fp significance
        pushf R0                        ;
        push AR1                        ;
        ldi @LRCIN,AR1                  ;
        ldi *AR1,R0                     ;
        and 0x10,R0                     ; this isolates the LRCIN bit
        bnz Lft                         ;
Rght    ldi @OUTSAMPLE_R,R0                   ;
        br Shift                        ;
Lft     ldi @OUTSAMPLE_L,R0                   ;
Shift
        lsh -12,R0                      ;
        sti R0,@S0_xdata                ;
        ldi 0,R5
        sti R5,@INSAMPLE_L
        sti R5,@INSAMPLE_R
        sti R5,@OUTSAMPLE_L
        sti R5,@OUTSAMPLE_R
        pop AR1                         ;
        popf R0                         ;
        pop R0                          ; restore significance
        pop ST                          ;
        reti                            ;

;-----------------------------
; RINT0 Interrupt Service Routine
;
RINT0   push ST                         ; Interrupt service routine
        push R0                         ; save fp significance
        pushf R0                        ;
        push AR1                        ;
        ldi @LRCIN,AR1                  ;
        ldi *AR1,R0                     ; Sample the LRCIN bit, and
then store the data in the right place
        and 0x10,R0                     ; isolated the LRCIN bit
        bnz left                        ;
right   ldi @S0_rdata,R0                ;
        sti R0,@INSAMPLE_R              ;
        br fin_int                      ;
left    ldi @S0_rdata,R0                ;
        sti R0,@INSAMPLE_L              ;
fin_int
        CALL INT_SER_L                  ;
        CALL INT_SER_R                  ;
        pop AR1                         ;
        popf R0                         ;
        pop R0                          ; restore significance
        pop ST                          ;
        reti                            ;
;----FIR ALgorithm Left Side-----------------------
INT_SER_L       ldi @INSAMPLE_L,R0

                float R0,R4
                stf R4,*AR2++%
                ldi @CO_ADDR,R2
                ldf 0.0,R0
                ldf 0.0,R3
                RPTS LENGTH - 1
                mpyf3 *R2--,*AR2++%,R0
           ||   ADDF3  R0,R3,R3
                ADDF3 R0,R3,R3
                fix R3,R3
                sti R3,@OUTSAMPLE_L

                rets
;----FIR Algorithm Left Side----------------------
INT_SER_R

              ldi @INSAMPLE_R,R0
              float R0,R4
              stf R4,*AR3++%
              ldi @CO_ADDR,R2
              ldf 0.0,R0
              ldf 0.0,R3
              RPTS LENGTH - 1
              mpyf3 *R2--,*AR3++%,R0
          ||  ADDF3  R0,R3,R3
              ADDF3 R0,R3,R3
              fix R3,R3
              sti R3,@OUTSAMPLE_R
                   
               rets

;---------------------------
; CODE TO INITIALISE THE TIMER AND SERIAL PORTS.
;-----------
; params for aic PCM3003 initialization ;
;---------
TIM0_PRD .word 4            ; (Fsys/2)/TIM0_PRD=TCKL0 (Fs =TCKL0/256)
S0_gctrl_val .word 0x0E970300           ; Serial port control register
values
S0_xctrl_val .word 0x00000111           ;
S0_rctrl_val .word 0x00000111           ;
;--------------------------------
XCLKSRCE .set 0 << 6                    ; 0=external 1= internal
RCLKSRCE .set 0 << 7                    ;
XVAREN .set 0 << 8                      ; VAREN 0 1
RVAREN .set 0 << 9                      ; FS ____---------_____
XFSM .set 0 <<10                        ; 0=burst 1=continuous
RFSM .set 0 <<11                        ;
CLKXP .set 1 <<12                       ;
CLKRP .set 1 <<13                       ;
DXP .set 0 <<14                         ;
DRP .set 0 <<15                         ;
FSXP .set 1 <<16                        ;
FSRP .set 1 <<17                        ;
XLEN .set 11b<<18                       ; 00=8 01 10$ 112
RLEN .set 11b<<20                       ;
EXTINT .set 0 <<22                      ;
EXINT .set 1 <<23                       ;
ERTINT .set 0 <<24                      ;
ERINT .set 1 <<25                       ;
S0 .sdef XCLKSRCE|RCLKSRCE|XVAREN|RVAREN|XFSM|RFSM|CLKXP|CLKRP ;
S0 .sdef S0|DXP|DRP|FSXP|FSRP|EXTINT|EXINT|ERTINT|ERINT ;
SPBITS .set 32                          ;
BITSEL .set ((SPBITS/8)-1) // 0=8, 1, 2$ and 32 bits ;
S0 .sdef S0|(BITSEL<<18)|(BITSEL<<20)   ;
S0gctrl_rst .word S0                    ;
S0gctrl_run .word S0|0x0C000000         ;
S0xctrl .set 0x00000111                 ;
S0rctrl .set 0x00000111                 ;
S0cpld .word 0x80A000                   ; CPLD status byte contains LRCIN

;------------
; initializes the serial port, codec and timers
; JP4
; Pins 1-2 16bit open; 32bit short
; Pins 3-4 DEM1 short to pullup (Deemphasis 1)
; Pins 5-6 DEM0 short to pullup (Deemphasis 0)
; JP1
; Pins 1-2 short to AVDD Mic channel 1
; Pins 3-4 short to AVDD Mic channel 2
;---------------
_SQRMODE .word 0x0              ;0x10
AICINIT ldi 0,R0             ; halt the timer
        sti R0,@T0_ctrl         ;
        ldi @TIM0_PRD,R0        ; put a count in prd
        sti R0,@T0_prd          ;
        ldi 0x283,R0            ; set bits to start timer
        or @_SQRMODE,R0
        sti R0,@T0_ctrl         ; timer is now running!
        ldi 0,R0                ;
        sti R0,@T0_count        ; T0_count = 0
;------------------------------
        ldi S0xctrl,R0          ; Init xmit/recv pin control
        sti R0,@S0_xctrl        ; S0_xctrl = S0xctrl
                                ; transmit control
        ldi S0rctrl,R0          ;
        sti R0,@S0_rctrl        ; S0_rctrl = S0rctrl
                                ; receive control
        ldi @S0gctrl_rst,R0     ; Reset serial port
        sti R0,@S0_gctrl        ; S0_gctrl = S0gctrl_rst
        ldi @S0gctrl_run,R0     ; Run serial port
        sti R0,@S0_gctrl        ; S0_gctrl = S0gctrl_run
        ldi 0,R0                ;
        sti R0,@S0_xdata        ;
        sti R0,@S0_rdata        ;
        sti R0,@INSAMPLE_L      ;
        sti R0,@INSAMPLE_R      ;
        STI R0,@OUTSAMPLE_L     ;
        STI R0,@OUTSAMPLE_R     ;
        rets                    ; return from subroutine

;-------------
; STACK
;------------
stack   .word   $+1                     ; the word at stack is the
address of the next cell
                                        ; Now install the interrupt vector

        .sect "int_vects"               ; name the section something
        br XINT0                        ;
        br RINT0                        ;
        .end
trl = S0gctrl_rst
        ldi @S0gctrl_run,R0     ; Run serial port
        sti R0,@S0_gctrl        ; S0_gctrl = S0gctrl_run
        ldi 0,R0                ;
        sti R0,@S0_xdata        ;
        sti R0,@S0_rdata        ;
        sti R0,@INSAMPLE_L      ;
        sti R0,@INSAMPLE_R      ;
        STI R0,@OUTSAMPLE_L     ;
        STI R0,@OUTSAMPLE_R     ;
        rets                    ; return from subroutine

;-------------
; STACK
;------------
stack   .word   $+1                     ; the word at stack is the
address of the next cell
                                        ; Now install the interrupt vector

        .sect "int_vects"               ; name the section something
        br XINT0                        ;
        br RINT0                        ;
        .end



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