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Good day. Happy Thanksgiving to those cebrating this occassion! From the CPLD control register 2, the FLASHENB bit will determine whether the external memory is FLASH or SRAM. Does that mean that FLASH & SRAM cannot be enable at the same time? FLASH has a 7 wait-state latency & SRAM has a 1 wait-state latency. Upon power up, i like to copy the program from FLASH to SRAM so that the on-chip DARAM can be utilise. Any suggestion? Thanks & regards, Doreen |
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C5402 DSK external memory
Started by ●November 24, 2000
Reply by ●November 27, 20002000-11-27
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You could copy a block at a time from Flash to internal DARAM, flip the FLASHENB bit, and copy the block from DARAM to SRAM. This is the only way I can think of doing it. Tony ----- Original Message ----- From: Doreen Yeo Lee Guek <> To: <> Sent: Friday, November 24, 2000 2:34 AM Subject: [c54x] C5402 DSK external memory > Good day. Happy Thanksgiving to those cebrating this occassion! > > >From the CPLD control register 2, the FLASHENB bit will determine whether > the external memory is FLASH or SRAM. Does that mean that FLASH & SRAM > cannot be enable at the same time? FLASH has a 7 wait-state latency & SRAM > has a 1 wait-state latency. Upon power up, i like to copy the program from > FLASH to SRAM so that the on-chip DARAM can be utilise. Any suggestion? > > Thanks & regards, > Doreen > > To Join: Send an email to > > To Post: Send an email to > > To Leave: Send an email to > > Archives: http://www.egroups.com/group/c54x > > Other Groups: http://www.dsprelated.com |
