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I'm attempting to use the CLK generator to produce a 2 MHZ bit clock and a Frame sync. I'm programming the SRGR[1..2], PCR, SPCR[1..2] registers. I've done my best to ensure that the reset procedure with GRST is followed according to Vol 5 Enhanced Peripherals document. 1) PCR FSXM, FSRM, CLKXM and CLKRM = set 2) SPCR2 FREE = set. I'm using BDM debugger I cant seem to get the clock to turn on and be visible to the outside world. Can anyone see something that I'm missing? Thanks Jason |
McBSP Programmable clock and Generator
Started by ●December 20, 2004
