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Hello, I am using the C5402 DSK board and we want to use an external interrupt to the DSP from the daughter board interface (X_INT0#) which maps to INT0# on the DSP in the Interrupt Flag Register (IFR). After going though all of the documentation for the timing of the interrupt pulse in the CPU and Peripherals (SPRU1331G) the only example with a timing diagram we've found for interrupt pulse durations is when the CPU is transitioning from a IDLE3 state, which indicates that the interrupt pulse needs to be at least 10 ns (1 clock period at 100 MHz). No details are provided for when/how the interrupt is latched(?) into the IFR (i.e., edge triggered, or do you just need to have a hold time of >10 ns). My interrupt pulse width will be 122 ns. Does anyone know where a good timing diagram might exist in the TI documentation and/or whether my proposed interrupt pulse width is acceptable? Thank you, -Todd Todd Goldsmith Principal Engineer Acoustic Technologies, Inc. 1620 South Stapley Drive, Suite 201 Mesa, Arizona 85204 Ph (480)507-4378 Fax (480)507-4399 |
External interrupt pulse width required for C5402 DSK External Daughter Board Interrupts
Started by ●November 14, 2001
