TMS320C5409 EVM hold time problem

Started by Dozio March 13, 2002
I'm developing a small Output port for the C5409 EVM. As output port I
use a standard LVC273 and this is not a problem. But when I checked the
timing (I/O PORT WRITE) I notice that the hold time of the DATA-BUS
after a the STROBE (IOSTRB#) is only 2ns (worst case value at 100MHz
clk). Is difficult to find a GATE (OR) that have only 2 ns delay time.
So I looked the EVM schematics and I notice that on the board the use a
standard GAL 5ns to generate the chip-selects of the external memories
and I/O !!! At 100Mhz and at worst case it shouldn't work !!!
Is the hold-time ( th(D)IOW )given by the datasheet (5409) wrong ?
Thanks for your help

Gian Carlo