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Hello, I am expanding C5402 memory with 8ns SRAM. I plan to use 0 wait state to gain high MIPS. All SRAM signals are directly connected to DSP and no GAL/CPLD is involved (CS=MSTRB). According to the data sheet. ta(MSTRBL)<=2H-8 ns. This maps to 2Hns or 67MHz. Anyone has reliably run it @80MHz? Thanks for sharing with me your experiences. Xiang Wei |
External SRAM speed limit with C5402
Started by ●May 29, 2002
