External SRAM speed limit with C5402

Started by xiang4413 May 29, 2002

I am expanding C5402 memory with 8ns SRAM. I plan to use 0 wait state
to gain high MIPS. All SRAM signals are directly connected to DSP and
no GAL/CPLD is involved (CS=MSTRB).

According to the data sheet. ta(MSTRBL)<=2H-8 ns. This maps to
2Hns or 67MHz. Anyone has reliably run it @80MHz? Thanks for
sharing with me your experiences.

Xiang Wei