using McBSP as GPIO pin on DSK5509

Hi,

I have configured McBSP1 pins DX1, DR1, FSX1, CLKX1 on DSK5509 as GPIO pins. In order to communication with external RF chip I needed to drive CLKX1 functioned as clock. It successfully worked by writing feild CLKXP in register PCR high and then low. However, the frequency of this clock is about 0.4MHz. Does there has any method to rise the clock frequency up to about 10MHz? I tried changing CLKGDV feild in SRGR10 to speedup sample rate generator's frequency, but it did not work. And also in TI's McBSP reference guide, nothing has memtioned about my problem. Thanks for your help!
Following is my McBSP setting, and how I construct out the clock signal.

MCBSP_Config gpio = {
0x0000, /* Serial Port Control Register 1 */
0x0000, /* Serial Port Control Register 2 */
0x0000, /* Receive Control Register 1 */
0x0000, /* Receive Control Register 2 */
0x0000, /* Transmit Control Register 1 */
0x0000, /* Transmit Control Register 2 */
0x000f, /* Sample Rate Generator Register 1 */
0x2000, /* Sample Rate Generator Register 2 */
0x0000, /* Multichannel Control Register 1 */
0x0000, /* Multichannel Control Register 2 */
0x3a00, /* Pin Control Register */
0x0000, /* Receive Channel Enable Register Partition A */
0x0000, /* Receive Channel Enable Register Partition B */
0x0000, /* Receive Channel Enable Register Partition C */
0x0000, /* Receive Channel Enable Register Partition D */
0x0000, /* Receive Channel Enable Register Partition E */
0x0000, /* Receive Channel Enable Register Partition F */
0x0000, /* Receive Channel Enable Register Partition G */
0x0000, /* Receive Channel Enable Register Partition H */
0x0000, /* Transmit Channel Enable Register Partition A */
0x0000, /* Transmit Channel Enable Register Partition B */
0x0000, /* Transmit Channel Enable Register Partition C */
0x0000, /* Transmit Channel Enable Register Partition D */
0x0000, /* Transmit Channel Enable Register Partition E */
0x0000, /* Transmit Channel Enable Register Partition F */
0x0000, /* Transmit Channel Enable Register Partition G */
0x0000 /* Transmit Channel Enable Register Partition H */
};

MCBSP_FSET(PCR1, CLKXP, 0) ;
MCBSP_FSET(PCR1, CLKXP, 1) ;

I'm appreciate for any help, thanks a lot!

Best regards,
SJ Hsu Start a New Thread

SJ Hsu-

> I have configured McBSP1 pins DX1, DR1, FSX1, CLKX1 on DSK5509 as
> GPIO pins. In order to communication with external RF chip I needed
> to drive CLKX1 functioned as clock. It successfully worked by writing
> feild CLKXP in register PCR high and then low. However, the frequency
> of this clock is about 0.4MHz. Does there has any method to rise the
> clock frequency up to about 10MHz? I tried changing CLKGDV feild in
> SRGR10 to speedup sample rate generator's frequency, but it did not
> work. And also in TI's McBSP reference guide, nothing has memtioned
> about my problem. Thanks for your help!

You should be able to get a decent rate out of CLKX by using CLKGDV. For example, if
your 5509A CPU frequency is 200 MHz, then the sample-rate generator clock source is
half and if you set CLKGDV to 5, then you should get 10 MHz.

I would suggest to debug the internal sample rate generator method and try to get it
working. You must have some other bits set incorrectly. Did you make sure that CLKX
is set for internal (i.e. output)? And you disabled GPIO for CLKX pin?

-Jeff
> Following is my McBSP setting, and how I construct out the clock signal.
>
> MCBSP_Config gpio = {
> 0x0000, /* Serial Port Control Register 1 */
> 0x0000, /* Serial Port Control Register 2 */
> 0x0000, /* Receive Control Register 1 */
> 0x0000, /* Receive Control Register 2 */
> 0x0000, /* Transmit Control Register 1 */
> 0x0000, /* Transmit Control Register 2 */
> 0x000f, /* Sample Rate Generator Register 1 */
> 0x2000, /* Sample Rate Generator Register 2 */
> 0x0000, /* Multichannel Control Register 1 */
> 0x0000, /* Multichannel Control Register 2 */
> 0x3a00, /* Pin Control Register */
> 0x0000, /* Receive Channel Enable Register Partition A */
> 0x0000, /* Receive Channel Enable Register Partition B */
> 0x0000, /* Receive Channel Enable Register Partition C */
> 0x0000, /* Receive Channel Enable Register Partition D */
> 0x0000, /* Receive Channel Enable Register Partition E */
> 0x0000, /* Receive Channel Enable Register Partition F */
> 0x0000, /* Receive Channel Enable Register Partition G */
> 0x0000, /* Receive Channel Enable Register Partition H */
> 0x0000, /* Transmit Channel Enable Register Partition A */
> 0x0000, /* Transmit Channel Enable Register Partition B */
> 0x0000, /* Transmit Channel Enable Register Partition C */
> 0x0000, /* Transmit Channel Enable Register Partition D */
> 0x0000, /* Transmit Channel Enable Register Partition E */
> 0x0000, /* Transmit Channel Enable Register Partition F */
> 0x0000, /* Transmit Channel Enable Register Partition G */
> 0x0000 /* Transmit Channel Enable Register Partition H */
> };
>
> MCBSP_FSET(PCR1, CLKXP, 0) ;
> MCBSP_FSET(PCR1, CLKXP, 1) ;
>
> I'm appreciate for any help, thanks a lot! Start a New Thread

SJ Hsu-

> I tried to change the CLKGDV, but the output rate of clock did not change. I also checked the sample rate
> generator registers, but I doubted that while I configured McBSP as GPIO, the CLKX pin's operation will not use
> sample rate generator anymore.
> Also I tried to configure PLL and rise the cpu clock up to 144MHz (measuring CLKOUT pin), the software
> clock seems
> become more fast, rise to 1.25MHz, i.e. 10 times than before, where the cpu clock is 12 MHz in before situation.
> Altough it becomes faster, but it still not reach the 10Mhz...

First, please reply to the group, not to me. My job does only permits me to reply to individual requests for help via
online forum or discussion group.

Second, you need to get the CPU clock working first. Obviously at 12 MHz CPU clock you're not going to get 10 MHz out
on CLKGDV, so what's the point of asking. There should be no "tried" or "seems" about this -- it either works or it
doesn't. You should be able to change CLKMD pins (or register) and get the correct PLL multiplier.

If you need 144 MHz CLKOUT, then you need to get that established first, then worry about serial port. Please report
again when you have measured CLKOUT to be *exactly* the rate that you will use for your project.

-Jeff

> Jeff Brower G
> SJ Hsu-
>
>> I have configured McBSP1 pins DX1, DR1, FSX1, CLKX1 on DSK5509 as
>> GPIO pins. In order to communication with external RF chip I needed
>> to drive CLKX1 functioned as clock. It successfully worked by writing
>> feild CLKXP in register PCR high and then low. However, the frequency
>> of this clock is about 0.4MHz. Does there has any method to rise the
>> clock frequency up to about 10MHz? I tried changing CLKGDV feild in
>> SRGR10 to speedup sample rate generator's frequency, but it did not
>> work. And also in TI's McBSP reference guide, nothing has memtioned
>> about my problem. Thanks for your help!
>
> You should be able to get a decent rate out of CLKX by using CLKGDV. For example, if
> your 5509A CPU frequency is 200 MHz, then the sample-rate generator clock source is
> half and if you set CLKGDV to 5, then you should get 10 MHz.
>
> I would suggest to debug the internal sample rate generator method and try to get it
> working. You must have some other bits set incorrectly. Did you make sure that CLKX
> is set for internal (i.e. output)? And you disabled GPIO for CLKX pin?
>
> -Jeff
>> Following is my McBSP setting, and how I construct out the clock signal.
>>
>> MCBSP_Config gpio = {
>> 0x0000, /* Serial Port Control Register 1 */
>> 0x0000, /* Serial Port Control Register 2 */
>> 0x0000, /* Receive Control Register 1 */
>> 0x0000, /* Receive Control Register 2 */
>> 0x0000, /* Transmit Control Register 1 */
>> 0x0000, /* Transmit Control Register 2 */
>> 0x000f, /* Sample Rate Generator Register 1 */
>> 0x2000, /* Sample Rate Generator Register 2 */
>> 0x0000, /* Multichannel Control Register 1 */
>> 0x0000, /* Multichannel Control Register 2 */
>> 0x3a00, /* Pin Control Register */
>> 0x0000, /* Receive Channel Enable Register Partition A */
>> 0x0000, /* Receive Channel Enable Register Partition B */
>> 0x0000, /* Receive Channel Enable Register Partition C */
>> 0x0000, /* Receive Channel Enable Register Partition D */
>> 0x0000, /* Receive Channel Enable Register Partition E */
>> 0x0000, /* Receive Channel Enable Register Partition F */
>> 0x0000, /* Receive Channel Enable Register Partition G */
>> 0x0000, /* Receive Channel Enable Register Partition H */
>> 0x0000, /* Transmit Channel Enable Register Partition A */
>> 0x0000, /* Transmit Channel Enable Register Partition B */
>> 0x0000, /* Transmit Channel Enable Register Partition C */
>> 0x0000, /* Transmit Channel Enable Register Partition D */
>> 0x0000, /* Transmit Channel Enable Register Partition E */
>> 0x0000, /* Transmit Channel Enable Register Partition F */
>> 0x0000, /* Transmit Channel Enable Register Partition G */
>> 0x0000 /* Transmit Channel Enable Register Partition H */
>> };
>>
>> MCBSP_FSET(PCR1, CLKXP, 0) ;
>> MCBSP_FSET(PCR1, CLKXP, 1) ;
>>
>> I'm appreciate for any help, thanks a lot!
>
> +++++++++++++++++++++++++++++++++++++++++++++++++
> Shuo-Jen Hsu, Graduate Student,
> Department of Electrical and Control Engineering,
> National Chiao-Tung University
> Hsinchu,Taiwan, ROC
> Tel: +886-3-5712121 ext:54427
> Email: h...@yahoo.com.tw
> +++++++++++++++++++++++++++++++++++++++++++++++++
> ϥΩUHgPANHJeANzwqUHH󪽱RAp@ӴNiOUHдoC Start a New Thread

SJ Hsu-

> I'm sorry I did not do what you said. I will follow your statement
> next time. Here I want to propose a solution about it. To configure
> PLL is a good way to increase the clock speed. I also use the
> following codes instead of original code.
> #define PCR1 (*(volatile ioport unsigned short*)0x2c12)
> PCR1 = 0x3a02;
> PCR1 = 0x3a00;
> In this way the GPIO which configured from McBSP will act more
> faster than calling McBSP macro.

Well, using "manual" GPIO instructions may get faster, but you will probably still
not reach 10 MHz. One problem with doing it manually is that the onchip CPU
core-to-external I/O interface will exhibit stalls that limit you to about 15 cycles
per GPIO "bit change" instruction, or in your case 15 x 7 nsec (144 MHz clock) --
which is still less than 10 MHz.

Another problem with manual method is that it takes all your processing time! What
about the rest of your real-time algorithm?

I think you will have to use the CLKGDV method. This is the correct way and should
work, assuming you can get the correct CPU clock rate established.

-Jeff

> --- In c..., "Jeff Brower" wrote:
> >
> > SJ Hsu-
> >
> > > I tried to change the CLKGDV, but the output rate of clock
> did not change. I also checked the sample rate
> > > generator registers, but I doubted that while I configured McBSP
> as GPIO, the CLKX pin's operation will not use
> > > sample rate generator anymore.
> > > Also I tried to configure PLL and rise the cpu clock up to
> 144MHz (measuring CLKOUT pin), the software
> > > clock seems
> > > become more fast, rise to 1.25MHz, i.e. 10 times than before,
> where the cpu clock is 12 MHz in before situation.
> > > Altough it becomes faster, but it still not reach the
> 10Mhz...
> >
> > First, please reply to the group, not to me. My job does only
> permits me to reply to individual requests for help via
> > online forum or discussion group.
> >
> > Second, you need to get the CPU clock working first. Obviously at
> 12 MHz CPU clock you're not going to get 10 MHz out
> > on CLKGDV, so what's the point of asking. There should be
> no "tried" or "seems" about this -- it either works or it
> > doesn't. You should be able to change CLKMD pins (or register)
> and get the correct PLL multiplier.
> >
> > If you need 144 MHz CLKOUT, then you need to get that established
> first, then worry about serial port. Please report
> > again when you have measured CLKOUT to be *exactly* the rate that
> you will use for your project.
> >
> > -Jeff
> >
> > > Jeff Brower G
> > > SJ Hsu-
> > >
> > >> I have configured McBSP1 pins DX1, DR1, FSX1, CLKX1 on DSK5509
> as
> > >> GPIO pins. In order to communication with external RF chip I
> needed
> > >> to drive CLKX1 functioned as clock. It successfully worked by
> writing
> > >> feild CLKXP in register PCR high and then low. However, the
> frequency
> > >> of this clock is about 0.4MHz. Does there has any method to
> rise the
> > >> clock frequency up to about 10MHz? I tried changing CLKGDV
> feild in
> > >> SRGR10 to speedup sample rate generator's frequency, but it did
> not
> > >> work. And also in TI's McBSP reference guide, nothing has
> memtioned
> > >> about my problem. Thanks for your help!
> > >
> > > You should be able to get a decent rate out of CLKX by using
> CLKGDV. For example, if
> > > your 5509A CPU frequency is 200 MHz, then the sample-rate
> generator clock source is
> > > half and if you set CLKGDV to 5, then you should get 10 MHz.
> > >
> > > I would suggest to debug the internal sample rate generator
> method and try to get it
> > > working. You must have some other bits set incorrectly. Did you
> make sure that CLKX
> > > is set for internal (i.e. output)? And you disabled GPIO for
> CLKX pin?
> > >
> > > -Jeff
> > >
> > >
> > >> Following is my McBSP setting, and how I construct out the
> clock signal.
> > >>
> > >> MCBSP_Config gpio = {
> > >> 0x0000, /* Serial Port Control Register 1 */
> > >> 0x0000, /* Serial Port Control Register 2 */
> > >> 0x0000, /* Receive Control Register 1 */
> > >> 0x0000, /* Receive Control Register 2 */
> > >> 0x0000, /* Transmit Control Register 1 */
> > >> 0x0000, /* Transmit Control Register 2 */
> > >> 0x000f, /* Sample Rate Generator Register 1 */
> > >> 0x2000, /* Sample Rate Generator Register 2 */
> > >> 0x0000, /* Multichannel Control Register 1 */
> > >> 0x0000, /* Multichannel Control Register 2 */
> > >> 0x3a00, /* Pin Control Register */
> > >> 0x0000, /* Receive Channel Enable Register Partition A */
> > >> 0x0000, /* Receive Channel Enable Register Partition B */
> > >> 0x0000, /* Receive Channel Enable Register Partition C */
> > >> 0x0000, /* Receive Channel Enable Register Partition D */
> > >> 0x0000, /* Receive Channel Enable Register Partition E */
> > >> 0x0000, /* Receive Channel Enable Register Partition F */
> > >> 0x0000, /* Receive Channel Enable Register Partition G */
> > >> 0x0000, /* Receive Channel Enable Register Partition H */
> > >> 0x0000, /* Transmit Channel Enable Register Partition A */
> > >> 0x0000, /* Transmit Channel Enable Register Partition B */
> > >> 0x0000, /* Transmit Channel Enable Register Partition C */
> > >> 0x0000, /* Transmit Channel Enable Register Partition D */
> > >> 0x0000, /* Transmit Channel Enable Register Partition E */
> > >> 0x0000, /* Transmit Channel Enable Register Partition F */
> > >> 0x0000, /* Transmit Channel Enable Register Partition G */
> > >> 0x0000 /* Transmit Channel Enable Register Partition H */
> > >> };
> > >>
> > >> MCBSP_FSET(PCR1, CLKXP, 0) ;
> > >> MCBSP_FSET(PCR1, CLKXP, 1) ;
> > >>
> > >> I'm appreciate for any help, thanks a lot! Start a New Thread