Hello all,
I'm looking to interface SDRAM to the 5502. I've been
designing embedded systems for 25 years, but unfortunately
(or perhaps, fortunately :)) have never used any type of DRAM.
My question is this:
Is it possible to manually "bank" SDRAM devices like
you can with SRAMs? The 5502 EMIF spec (spru621f) states
that 256-Mbit is the largest device that can be used.
Can I use, say, 2 of these devices, and add some
logic to manually route the chip select signal to one
or the other?
I suspect this cannot be done due to the refresh requirements,
but I would like to get some of your thoughts on this.
Thanks,
Tony
SDRAM - General question
Started by ●March 17, 2009
Reply by ●March 18, 20092009-03-18
Hi Tony,
Have you already considered that 16-bit or 32-bit memory will
technically get you beyond the 256M limit? I'm not sure that I
understand everything involved, but I think you could get 1GB of DRAM
going in a 32-bit EMIF setup. The 5506 that I am working with would
be limited to 512MB because of its 16-bit EMIF limitations, but I
happen to not need DRAM for this project.
In other words, I think you could, in fact, use two of these chips,
and connect them each to different byte enable pins on the EMIF. You
could even use four of them.
Brian Willoughby
Sound Consulting
On Mar 16, 2009, at 07:50, tonyzlr wrote:
> I'm looking to interface SDRAM to the 5502. I've been
> designing embedded systems for 25 years, but unfortunately
> (or perhaps, fortunately :)) have never used any type of DRAM.
>
> My question is this:
> Is it possible to manually "bank" SDRAM devices like
> you can with SRAMs? The 5502 EMIF spec (spru621f) states
> that 256-Mbit is the largest device that can be used.
> Can I use, say, 2 of these devices, and add some
> logic to manually route the chip select signal to one
> or the other?
>
> I suspect this cannot be done due to the refresh requirements,
> but I would like to get some of your thoughts on this.
Have you already considered that 16-bit or 32-bit memory will
technically get you beyond the 256M limit? I'm not sure that I
understand everything involved, but I think you could get 1GB of DRAM
going in a 32-bit EMIF setup. The 5506 that I am working with would
be limited to 512MB because of its 16-bit EMIF limitations, but I
happen to not need DRAM for this project.
In other words, I think you could, in fact, use two of these chips,
and connect them each to different byte enable pins on the EMIF. You
could even use four of them.
Brian Willoughby
Sound Consulting
On Mar 16, 2009, at 07:50, tonyzlr wrote:
> I'm looking to interface SDRAM to the 5502. I've been
> designing embedded systems for 25 years, but unfortunately
> (or perhaps, fortunately :)) have never used any type of DRAM.
>
> My question is this:
> Is it possible to manually "bank" SDRAM devices like
> you can with SRAMs? The 5502 EMIF spec (spru621f) states
> that 256-Mbit is the largest device that can be used.
> Can I use, say, 2 of these devices, and add some
> logic to manually route the chip select signal to one
> or the other?
>
> I suspect this cannot be done due to the refresh requirements,
> but I would like to get some of your thoughts on this.
Reply by ●March 19, 20092009-03-19
Brian-
> Have you already considered that 16-bit or 32-bit memory will
> technically get you beyond the 256M limit? I'm not sure that I
> understand everything involved, but I think you could get 1GB of DRAM
> going in a 32-bit EMIF setup. The 5506 that I am working with would
> be limited to 512MB because of its 16-bit EMIF limitations, but I
> happen to not need DRAM for this project.
>
> In other words, I think you could, in fact, use two of these chips,
> and connect them each to different byte enable pins on the EMIF. You
> could even use four of them.
C55xx devices expect EMIF_BEn pins to be connected to byte enables on the SDRAM.
There may be a way to get beyond TI's stated 256 Mbit limit, but altering the
intended use of the byte enable pins is likely not the way.
-Jeff
> On Mar 16, 2009, at 07:50, tonyzlr wrote:
> > I'm looking to interface SDRAM to the 5502. I've been
> > designing embedded systems for 25 years, but unfortunately
> > (or perhaps, fortunately :)) have never used any type of DRAM.
> >
> > My question is this:
> > Is it possible to manually "bank" SDRAM devices like
> > you can with SRAMs? The 5502 EMIF spec (spru621f) states
> > that 256-Mbit is the largest device that can be used.
> > Can I use, say, 2 of these devices, and add some
> > logic to manually route the chip select signal to one
> > or the other?
> >
> > I suspect this cannot be done due to the refresh requirements,
> > but I would like to get some of your thoughts on this.
> Have you already considered that 16-bit or 32-bit memory will
> technically get you beyond the 256M limit? I'm not sure that I
> understand everything involved, but I think you could get 1GB of DRAM
> going in a 32-bit EMIF setup. The 5506 that I am working with would
> be limited to 512MB because of its 16-bit EMIF limitations, but I
> happen to not need DRAM for this project.
>
> In other words, I think you could, in fact, use two of these chips,
> and connect them each to different byte enable pins on the EMIF. You
> could even use four of them.
C55xx devices expect EMIF_BEn pins to be connected to byte enables on the SDRAM.
There may be a way to get beyond TI's stated 256 Mbit limit, but altering the
intended use of the byte enable pins is likely not the way.
-Jeff
> On Mar 16, 2009, at 07:50, tonyzlr wrote:
> > I'm looking to interface SDRAM to the 5502. I've been
> > designing embedded systems for 25 years, but unfortunately
> > (or perhaps, fortunately :)) have never used any type of DRAM.
> >
> > My question is this:
> > Is it possible to manually "bank" SDRAM devices like
> > you can with SRAMs? The 5502 EMIF spec (spru621f) states
> > that 256-Mbit is the largest device that can be used.
> > Can I use, say, 2 of these devices, and add some
> > logic to manually route the chip select signal to one
> > or the other?
> >
> > I suspect this cannot be done due to the refresh requirements,
> > but I would like to get some of your thoughts on this.
Reply by ●March 19, 20092009-03-19
Brian-
> > C55xx devices expect EMIF_BEn pins to be connected to byte enables
> > on the SDRAM.
> > There may be a way to get beyond TI's stated 256 Mbit limit, but
> > altering the
> > intended use of the byte enable pins is likely not the way.
>
> Sorry, I assumed that the SDRAM has only one byte enable pin.
> Perhaps because I am thinking of 1-bit, 4-bit, and 8-bit DRAM memory
> chips. If you have a 16-bit or 32-bit chip, then you would need to
> use multiple enables on one chip, and thus they would not be able to
> be used for other chips.
>
> Here's what I was thinking: An 8-bit 256 MB chip used in a group of
> four. Maybe you could tell me what SDRAM chip you're looking at, and
> I could look at it in detail.
>
> I also notice that you're saying 256 Mbit, so my mention of 256 MB is
> probably wrong, too.
>
> Here's another shot in the dark: The 5506 has four distinct memory
> spaces. Could you use multiple SDRAM chips by placing each in its
> own memory space? The EMIF select pins for each memory space could
> then enable individual 256 Mbit chips.
I seem to recall the TI docs say somewhere that C55x EMIF supports SDRAM in only one
memory space. I think otherwise the chip would need more than one SDRAM controller.
This is probably common to both C5x and C6x series, for example some C64x devices
have two EMIFs to handle more than one "SDRAM type" of memory. On C64x, I think
another memory space can contain a synchronous memory, such as sync burst RAM,
simultaneously with SDRAM, but I don't think two SDRAMs. I could be wrong!
-Jeff
> > C55xx devices expect EMIF_BEn pins to be connected to byte enables
> > on the SDRAM.
> > There may be a way to get beyond TI's stated 256 Mbit limit, but
> > altering the
> > intended use of the byte enable pins is likely not the way.
>
> Sorry, I assumed that the SDRAM has only one byte enable pin.
> Perhaps because I am thinking of 1-bit, 4-bit, and 8-bit DRAM memory
> chips. If you have a 16-bit or 32-bit chip, then you would need to
> use multiple enables on one chip, and thus they would not be able to
> be used for other chips.
>
> Here's what I was thinking: An 8-bit 256 MB chip used in a group of
> four. Maybe you could tell me what SDRAM chip you're looking at, and
> I could look at it in detail.
>
> I also notice that you're saying 256 Mbit, so my mention of 256 MB is
> probably wrong, too.
>
> Here's another shot in the dark: The 5506 has four distinct memory
> spaces. Could you use multiple SDRAM chips by placing each in its
> own memory space? The EMIF select pins for each memory space could
> then enable individual 256 Mbit chips.
I seem to recall the TI docs say somewhere that C55x EMIF supports SDRAM in only one
memory space. I think otherwise the chip would need more than one SDRAM controller.
This is probably common to both C5x and C6x series, for example some C64x devices
have two EMIFs to handle more than one "SDRAM type" of memory. On C64x, I think
another memory space can contain a synchronous memory, such as sync burst RAM,
simultaneously with SDRAM, but I don't think two SDRAMs. I could be wrong!
-Jeff
Reply by ●March 20, 20092009-03-20
On Mar 19, 2009, at 15:34, Jeff Brower wrote:
> C55xx devices expect EMIF_BEn pins to be connected to byte enables
> on the SDRAM.
> There may be a way to get beyond TI's stated 256 Mbit limit, but
> altering the
> intended use of the byte enable pins is likely not the way.
Sorry, I assumed that the SDRAM has only one byte enable pin.
Perhaps because I am thinking of 1-bit, 4-bit, and 8-bit DRAM memory
chips. If you have a 16-bit or 32-bit chip, then you would need to
use multiple enables on one chip, and thus they would not be able to
be used for other chips.
Here's what I was thinking: An 8-bit 256 MB chip used in a group of
four. Maybe you could tell me what SDRAM chip you're looking at, and
I could look at it in detail.
I also notice that you're saying 256 Mbit, so my mention of 256 MB is
probably wrong, too.
Here's another shot in the dark: The 5506 has four distinct memory
spaces. Could you use multiple SDRAM chips by placing each in its
own memory space? The EMIF select pins for each memory space could
then enable individual 256 Mbit chips.
Again, sorry that I have never used SDRAM on the C55x. I'm just
reciting what I remember reading in the TI documentation for the
EMIF, of which there are a few flavors.
Brian
> C55xx devices expect EMIF_BEn pins to be connected to byte enables
> on the SDRAM.
> There may be a way to get beyond TI's stated 256 Mbit limit, but
> altering the
> intended use of the byte enable pins is likely not the way.
Sorry, I assumed that the SDRAM has only one byte enable pin.
Perhaps because I am thinking of 1-bit, 4-bit, and 8-bit DRAM memory
chips. If you have a 16-bit or 32-bit chip, then you would need to
use multiple enables on one chip, and thus they would not be able to
be used for other chips.
Here's what I was thinking: An 8-bit 256 MB chip used in a group of
four. Maybe you could tell me what SDRAM chip you're looking at, and
I could look at it in detail.
I also notice that you're saying 256 Mbit, so my mention of 256 MB is
probably wrong, too.
Here's another shot in the dark: The 5506 has four distinct memory
spaces. Could you use multiple SDRAM chips by placing each in its
own memory space? The EMIF select pins for each memory space could
then enable individual 256 Mbit chips.
Again, sorry that I have never used SDRAM on the C55x. I'm just
reciting what I remember reading in the TI documentation for the
EMIF, of which there are a few flavors.
Brian
Reply by ●March 20, 20092009-03-20
Hi Brian,
I see what you mean regarding using the byte enable lines
to access more than one SDRAM chip. I assume that, using
multiple SDRAM chips in this way, all chips would be
refreshed simultaneously by the 5502. Is this correct?
Tony
----- Original Message -----
From: Sound Consulting
To: c...
Sent: Wednesday, March 18, 2009 12:28 AM
Subject: Re: [c55x] SDRAM - General question
Hi Tony,
Have you already considered that 16-bit or 32-bit memory will
technically get you beyond the 256M limit? I'm not sure that I
understand everything involved, but I think you could get 1GB of DRAM
going in a 32-bit EMIF setup. The 5506 that I am working with would
be limited to 512MB because of its 16-bit EMIF limitations, but I
happen to not need DRAM for this project.
In other words, I think you could, in fact, use two of these chips,
and connect them each to different byte enable pins on the EMIF. You
could even use four of them.
Brian Willoughby
Sound Consulting
On Mar 16, 2009, at 07:50, tonyzlr wrote:
> I'm looking to interface SDRAM to the 5502. I've been
> designing embedded systems for 25 years, but unfortunately
> (or perhaps, fortunately :)) have never used any type of DRAM.
>
> My question is this:
> Is it possible to manually "bank" SDRAM devices like
> you can with SRAMs? The 5502 EMIF spec (spru621f) states
> that 256-Mbit is the largest device that can be used.
> Can I use, say, 2 of these devices, and add some
> logic to manually route the chip select signal to one
> or the other?
>
> I suspect this cannot be done due to the refresh requirements,
> but I would like to get some of your thoughts on this.
I see what you mean regarding using the byte enable lines
to access more than one SDRAM chip. I assume that, using
multiple SDRAM chips in this way, all chips would be
refreshed simultaneously by the 5502. Is this correct?
Tony
----- Original Message -----
From: Sound Consulting
To: c...
Sent: Wednesday, March 18, 2009 12:28 AM
Subject: Re: [c55x] SDRAM - General question
Hi Tony,
Have you already considered that 16-bit or 32-bit memory will
technically get you beyond the 256M limit? I'm not sure that I
understand everything involved, but I think you could get 1GB of DRAM
going in a 32-bit EMIF setup. The 5506 that I am working with would
be limited to 512MB because of its 16-bit EMIF limitations, but I
happen to not need DRAM for this project.
In other words, I think you could, in fact, use two of these chips,
and connect them each to different byte enable pins on the EMIF. You
could even use four of them.
Brian Willoughby
Sound Consulting
On Mar 16, 2009, at 07:50, tonyzlr wrote:
> I'm looking to interface SDRAM to the 5502. I've been
> designing embedded systems for 25 years, but unfortunately
> (or perhaps, fortunately :)) have never used any type of DRAM.
>
> My question is this:
> Is it possible to manually "bank" SDRAM devices like
> you can with SRAMs? The 5502 EMIF spec (spru621f) states
> that 256-Mbit is the largest device that can be used.
> Can I use, say, 2 of these devices, and add some
> logic to manually route the chip select signal to one
> or the other?
>
> I suspect this cannot be done due to the refresh requirements,
> but I would like to get some of your thoughts on this.
Reply by ●March 26, 20092009-03-26
Hi guys,
Sorry for the delay in following up on this thread, but I was
out of the office.
The more I read TI document spru621f, the more confused I get.
Looking at the EMIF CE size control register on page 2-95,
it looks like the
maximum number of addressable locations is 16M. You can address either
4M per CE in each of the 4 CE spaces, 8M per CE (CE0 & CE2), or
16M (CE0 only). So no matter how you cut it, 16M is the maximum
reach of the EMIF address space. Now, configuring for a 32-bit access,
that's 4 bytes per location, or 64Mbytes.
Now if you look at Table 2-11 on page 2-22, they show a configuration
where you can have 128MBytes of SDRAM. What am I missing?
TonyZ
On Mar 19, 2009, at 15:34, Jeff Brower wrote:
> C55xx devices expect EMIF_BEn pins to be connected to byte enables
> on the SDRAM.
> There may be a way to get beyond TI's stated 256 Mbit limit, but
> altering the
> intended use of the byte enable pins is likely not the way.
Sorry, I assumed that the SDRAM has only one byte enable pin.
Perhaps because I am thinking of 1-bit, 4-bit, and 8-bit DRAM memory
chips. If you have a 16-bit or 32-bit chip, then you would need to
use multiple enables on one chip, and thus they would not be able to
be used for other chips.
Here's what I was thinking: An 8-bit 256 MB chip used in a group of
four. Maybe you could tell me what SDRAM chip you're looking at, and
I could look at it in detail.
I also notice that you're saying 256 Mbit, so my mention of 256 MB is
probably wrong, too.
Here's another shot in the dark: The 5506 has four distinct memory
spaces. Could you use multiple SDRAM chips by placing each in its
own memory space? The EMIF select pins for each memory space could
then enable individual 256 Mbit chips.
Again, sorry that I have never used SDRAM on the C55x. I'm just
reciting what I remember reading in the TI documentation for the
EMIF, of which there are a few flavors.
Brian
Sorry for the delay in following up on this thread, but I was
out of the office.
The more I read TI document spru621f, the more confused I get.
Looking at the EMIF CE size control register on page 2-95,
it looks like the
maximum number of addressable locations is 16M. You can address either
4M per CE in each of the 4 CE spaces, 8M per CE (CE0 & CE2), or
16M (CE0 only). So no matter how you cut it, 16M is the maximum
reach of the EMIF address space. Now, configuring for a 32-bit access,
that's 4 bytes per location, or 64Mbytes.
Now if you look at Table 2-11 on page 2-22, they show a configuration
where you can have 128MBytes of SDRAM. What am I missing?
TonyZ
On Mar 19, 2009, at 15:34, Jeff Brower wrote:
> C55xx devices expect EMIF_BEn pins to be connected to byte enables
> on the SDRAM.
> There may be a way to get beyond TI's stated 256 Mbit limit, but
> altering the
> intended use of the byte enable pins is likely not the way.
Sorry, I assumed that the SDRAM has only one byte enable pin.
Perhaps because I am thinking of 1-bit, 4-bit, and 8-bit DRAM memory
chips. If you have a 16-bit or 32-bit chip, then you would need to
use multiple enables on one chip, and thus they would not be able to
be used for other chips.
Here's what I was thinking: An 8-bit 256 MB chip used in a group of
four. Maybe you could tell me what SDRAM chip you're looking at, and
I could look at it in detail.
I also notice that you're saying 256 Mbit, so my mention of 256 MB is
probably wrong, too.
Here's another shot in the dark: The 5506 has four distinct memory
spaces. Could you use multiple SDRAM chips by placing each in its
own memory space? The EMIF select pins for each memory space could
then enable individual 256 Mbit chips.
Again, sorry that I have never used SDRAM on the C55x. I'm just
reciting what I remember reading in the TI documentation for the
EMIF, of which there are a few flavors.
Brian
Reply by ●March 29, 20092009-03-29
Tony-
> Sorry for the delay in following up on this thread, but I was
> out of the office.
>
> The more I read TI document spru621f, the more confused I get.
> Looking at the EMIF CE size control register on page 2-95,
> it looks like the
> maximum number of addressable locations is 16M. You can address either
> 4M per CE in each of the 4 CE spaces, 8M per CE (CE0 & CE2), or
> 16M (CE0 only). So no matter how you cut it, 16M is the maximum
> reach of the EMIF address space. Now, configuring for a 32-bit access,
> that's 4 bytes per location, or 64Mbytes.
>
> Now if you look at Table 2-11 on page 2-22, they show a configuration
> where you can have 128MBytes of SDRAM. What am I missing?
I think "conflicts" tend to appear in TI tech data because the device is byte-addressable in program space, but only
word-addressable in data space. I'm sure TI has it straight but maybe not the rest of us.
I recall on some C55x projects we worked on here that we found it best to think of the address space as "word
addressable"; i.e. every address is 2 bytes. Any time we tried to think in terms of byte-addressable, we had problems
-- this included EEPROM addressing, SRAM access, etc. We loaded our code into external SRAM -- knew it started at
zero, some instructions are up to 6 bytes, and we relied on the i-cache to figure things out.
So if you put code into your SDRAM area then it should work but if you mix with data then you might get a headache :-)
-Jeff
> On Mar 19, 2009, at 15:34, Jeff Brower wrote:
>> C55xx devices expect EMIF_BEn pins to be connected to byte enables
>> on the SDRAM.
>> There may be a way to get beyond TI's stated 256 Mbit limit, but
>> altering the
>> intended use of the byte enable pins is likely not the way.
>
> Sorry, I assumed that the SDRAM has only one byte enable pin.
> Perhaps because I am thinking of 1-bit, 4-bit, and 8-bit DRAM memory
> chips. If you have a 16-bit or 32-bit chip, then you would need to
> use multiple enables on one chip, and thus they would not be able to
> be used for other chips.
>
> Here's what I was thinking: An 8-bit 256 MB chip used in a group of
> four. Maybe you could tell me what SDRAM chip you're looking at, and
> I could look at it in detail.
>
> I also notice that you're saying 256 Mbit, so my mention of 256 MB is
> probably wrong, too.
>
> Here's another shot in the dark: The 5506 has four distinct memory
> spaces. Could you use multiple SDRAM chips by placing each in its
> own memory space? The EMIF select pins for each memory space could
> then enable individual 256 Mbit chips.
>
> Again, sorry that I have never used SDRAM on the C55x. I'm just
> reciting what I remember reading in the TI documentation for the
> EMIF, of which there are a few flavors.
>
> Brian
>
>
> Sorry for the delay in following up on this thread, but I was
> out of the office.
>
> The more I read TI document spru621f, the more confused I get.
> Looking at the EMIF CE size control register on page 2-95,
> it looks like the
> maximum number of addressable locations is 16M. You can address either
> 4M per CE in each of the 4 CE spaces, 8M per CE (CE0 & CE2), or
> 16M (CE0 only). So no matter how you cut it, 16M is the maximum
> reach of the EMIF address space. Now, configuring for a 32-bit access,
> that's 4 bytes per location, or 64Mbytes.
>
> Now if you look at Table 2-11 on page 2-22, they show a configuration
> where you can have 128MBytes of SDRAM. What am I missing?
I think "conflicts" tend to appear in TI tech data because the device is byte-addressable in program space, but only
word-addressable in data space. I'm sure TI has it straight but maybe not the rest of us.
I recall on some C55x projects we worked on here that we found it best to think of the address space as "word
addressable"; i.e. every address is 2 bytes. Any time we tried to think in terms of byte-addressable, we had problems
-- this included EEPROM addressing, SRAM access, etc. We loaded our code into external SRAM -- knew it started at
zero, some instructions are up to 6 bytes, and we relied on the i-cache to figure things out.
So if you put code into your SDRAM area then it should work but if you mix with data then you might get a headache :-)
-Jeff
> On Mar 19, 2009, at 15:34, Jeff Brower wrote:
>> C55xx devices expect EMIF_BEn pins to be connected to byte enables
>> on the SDRAM.
>> There may be a way to get beyond TI's stated 256 Mbit limit, but
>> altering the
>> intended use of the byte enable pins is likely not the way.
>
> Sorry, I assumed that the SDRAM has only one byte enable pin.
> Perhaps because I am thinking of 1-bit, 4-bit, and 8-bit DRAM memory
> chips. If you have a 16-bit or 32-bit chip, then you would need to
> use multiple enables on one chip, and thus they would not be able to
> be used for other chips.
>
> Here's what I was thinking: An 8-bit 256 MB chip used in a group of
> four. Maybe you could tell me what SDRAM chip you're looking at, and
> I could look at it in detail.
>
> I also notice that you're saying 256 Mbit, so my mention of 256 MB is
> probably wrong, too.
>
> Here's another shot in the dark: The 5506 has four distinct memory
> spaces. Could you use multiple SDRAM chips by placing each in its
> own memory space? The EMIF select pins for each memory space could
> then enable individual 256 Mbit chips.
>
> Again, sorry that I have never used SDRAM on the C55x. I'm just
> reciting what I remember reading in the TI documentation for the
> EMIF, of which there are a few flavors.
>
> Brian
>
>
Reply by ●March 29, 20092009-03-29
Jeff,
Thanks for your insight. I simply want to use the SDRAM for data -
no programs will be running out of it. So as I understand you, if I
treat it as word-addressable, it might simplify matters. I'll take another
look at the spec and see what sense I can make of it.
Thanks again.
Tony
Tony-
> Sorry for the delay in following up on this thread, but I was
> out of the office.
>
> The more I read TI document spru621f, the more confused I get.
> Looking at the EMIF CE size control register on page 2-95,
> it looks like the
> maximum number of addressable locations is 16M. You can address either
> 4M per CE in each of the 4 CE spaces, 8M per CE (CE0 & CE2), or
> 16M (CE0 only). So no matter how you cut it, 16M is the maximum
> reach of the EMIF address space. Now, configuring for a 32-bit access,
> that's 4 bytes per location, or 64Mbytes.
>
> Now if you look at Table 2-11 on page 2-22, they show a configuration
> where you can have 128MBytes of SDRAM. What am I missing?
I think "conflicts" tend to appear in TI tech data because the device is byte-addressable in program space, but only
word-addressable in data space. I'm sure TI has it straight but maybe not the rest of us.
I recall on some C55x projects we worked on here that we found it best to think of the address space as "word
addressable"; i.e. every address is 2 bytes. Any time we tried to think in terms of byte-addressable, we had problems
-- this included EEPROM addressing, SRAM access, etc. We loaded our code into external SRAM -- knew it started at
zero, some instructions are up to 6 bytes, and we relied on the i-cache to figure things out.
So if you put code into your SDRAM area then it should work but if you mix with data then you might get a headache :-)
-Jeff
Thanks for your insight. I simply want to use the SDRAM for data -
no programs will be running out of it. So as I understand you, if I
treat it as word-addressable, it might simplify matters. I'll take another
look at the spec and see what sense I can make of it.
Thanks again.
Tony
Tony-
> Sorry for the delay in following up on this thread, but I was
> out of the office.
>
> The more I read TI document spru621f, the more confused I get.
> Looking at the EMIF CE size control register on page 2-95,
> it looks like the
> maximum number of addressable locations is 16M. You can address either
> 4M per CE in each of the 4 CE spaces, 8M per CE (CE0 & CE2), or
> 16M (CE0 only). So no matter how you cut it, 16M is the maximum
> reach of the EMIF address space. Now, configuring for a 32-bit access,
> that's 4 bytes per location, or 64Mbytes.
>
> Now if you look at Table 2-11 on page 2-22, they show a configuration
> where you can have 128MBytes of SDRAM. What am I missing?
I think "conflicts" tend to appear in TI tech data because the device is byte-addressable in program space, but only
word-addressable in data space. I'm sure TI has it straight but maybe not the rest of us.
I recall on some C55x projects we worked on here that we found it best to think of the address space as "word
addressable"; i.e. every address is 2 bytes. Any time we tried to think in terms of byte-addressable, we had problems
-- this included EEPROM addressing, SRAM access, etc. We loaded our code into external SRAM -- knew it started at
zero, some instructions are up to 6 bytes, and we relied on the i-cache to figure things out.
So if you put code into your SDRAM area then it should work but if you mix with data then you might get a headache :-)
-Jeff
