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TI JTAG signal integrity issue

Started by Jeff Brower September 20, 2013
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I'm posting this question here, the global knowledge source for TI JTAG related issues :-)

I have a batch of C5510A modules that are showing inconsistent JTAG scan test results. Out of 6, 3 are passing, two
with buffered TCK and RTCK, and 1 without (without = bypass the buffer using zero-ohm Rs). The failing modules also
are configured both ways. Due to this variation, I'm concerned that TCK/RTCK isn't the actual problem.

My question is how can I verify that JTAG is "trying to work", and thus it might be TCK related? SDConfig doesn't
allow this. Is there another utility? Below are some additional notes. Thanks.

-Jeff

1) Trace length from JTAG header to C5510A is less than 1".

2) Using dig scope, C5510 clocks are verified (27 MHz). /RESET timing has been verified. Power sequence has been
verified. Silicon revision is 2.2, so RST_MODE is ignored.

3) I can post any scope trace required. A scope capture for the buffered version is here:

http://signalogic.com/images/Signalogic_C5510_TCK_b4_after_buffer.jpg

4) Emulator is an XDS510-Plus.
Hi Jeff,

I do not have an answer that is specific to the symptoms you're
seeing. However, I would recommend double-checking the simple things
like power supply voltages. I had intermittent problems with XDS510
operations, particularly with regard to Reset. I found out that my
3.3 V supply was actually running closer to 4.0 V due to a bad I/O
chip. Thankfully, I fixed the error before shipping the product, and
as a side effect I noticed that all of my JTAG problems went away. I
can't believe none of the parts ever failed after being exposed to 4
V, but the incorrect operations were forgivable, considering.

Brian Willoughby
Sound Consulting
On Sep 20, 2013, at 11:55, Jeff Brower wrote:
> I have a batch of C5510A modules that are showing inconsistent JTAG
> scan test results. Out of 6, 3 are passing, two
> with buffered TCK and RTCK, and 1 without (without = bypass the
> buffer using zero-ohm Rs). The failing modules also
> are configured both ways. Due to this variation, I'm concerned that
> TCK/RTCK isn't the actual problem.
>
> My question is how can I verify that JTAG is "trying to work", and
> thus it might be TCK related? SDConfig doesn't
> allow this. Is there another utility? Below are some additional
> notes. Thanks.
>
> -Jeff
>
> 1) Trace length from JTAG header to C5510A is less than 1".
>
> 2) Using dig scope, C5510 clocks are verified (27 MHz). /RESET
> timing has been verified. Power sequence has been
> verified. Silicon revision is 2.2, so RST_MODE is ignored.
>
> 3) I can post any scope trace required. A scope capture for the
> buffered version is here:
>
> http://signalogic.com/images/Signalogic_C5510_TCK_b4_after_buffer.jpg
>
> 4) Emulator is an XDS510-Plus.
Brian-

Thanks very much for your reply. I think I've made some progress, see my C6x group reply.

-Jeff

> I do not have an answer that is specific to the symptoms you're
> seeing. However, I would recommend double-checking the simple things
> like power supply voltages. I had intermittent problems with XDS510
> operations, particularly with regard to Reset. I found out that my
> 3.3 V supply was actually running closer to 4.0 V due to a bad I/O
> chip. Thankfully, I fixed the error before shipping the product, and
> as a side effect I noticed that all of my JTAG problems went away. I
> can't believe none of the parts ever failed after being exposed to 4
> V, but the incorrect operations were forgivable, considering.
>
> Brian Willoughby
> Sound Consulting
> On Sep 20, 2013, at 11:55, Jeff Brower wrote:
>> I have a batch of C5510A modules that are showing inconsistent JTAG
>> scan test results. Out of 6, 3 are passing, two
>> with buffered TCK and RTCK, and 1 without (without = bypass the
>> buffer using zero-ohm Rs). The failing modules also
>> are configured both ways. Due to this variation, I'm concerned that
>> TCK/RTCK isn't the actual problem.
>>
>> My question is how can I verify that JTAG is "trying to work", and
>> thus it might be TCK related? SDConfig doesn't
>> allow this. Is there another utility? Below are some additional
>> notes. Thanks.
>>
>> -Jeff
>>
>> 1) Trace length from JTAG header to C5510A is less than 1".
>>
>> 2) Using dig scope, C5510 clocks are verified (27 MHz). /RESET
>> timing has been verified. Power sequence has been
>> verified. Silicon revision is 2.2, so RST_MODE is ignored.
>>
>> 3) I can post any scope trace required. A scope capture for the
>> buffered version is here:
>>
>> http://signalogic.com/images/Signalogic_C5510_TCK_b4_after_buffer.jpg
>>
>> 4) Emulator is an XDS510-Plus.