Re: [c6x] TI JTAG signal integrity issue
> 1. Is the problem frequency sensitive?? 5,10, 15 Mhz??
> 2. I think that SDconfig has a diagnostic mode - does it fail in the
> same place??
> 3. Have you tried selecting a 55or AA pattern and scoped it?? [maybe
> that is the missing image??]
> 4. A bit hokey but have you tried 2 scope probes on TCLK?? for just a
> bit of extra capacitance
> 5. Do the failing units identify the IR length??
Yes I did try these variations and tests.
On one of the modules I was able to intermittently pass JTAG scan test by varying (a lot) the temperature of the PCB
and/or applying pressure to the chip. It looks to me that somehow this batch of modules has been through extreme
temperature cycling and suffered at least some (and probably several) fractured solder joints. I will need to talk to
the customer :-)
Thanks everyone for your help.
> On 9/20/2013 1:55 PM, Jeff Brower wrote:
>> I'm posting this question here, the global knowledge source for TI
>> JTAG related issues :-)
>> I have a batch of C5510A modules that are showing inconsistent JTAG
>> scan test results. Out of 6, 3 are passing, two
>> with buffered TCK and RTCK, and 1 without (without = bypass the buffer
>> using zero-ohm Rs). The failing modules also
>> are configured both ways. Due to this variation, I'm concerned that
>> TCK/RTCK isn't the actual problem.
>> My question is how can I verify that JTAG is "trying to work", and
>> thus it might be TCK related? SDConfig doesn't
>> allow this. Is there another utility? Below are some additional notes.
>> 1) Trace length from JTAG header to C5510A is less than 1".
>> 2) Using dig scope, C5510 clocks are verified (27 MHz). /RESET timing
>> has been verified. Power sequence has been
>> verified. Silicon revision is 2.2, so RST_MODE is ignored.
>> 3) I can post any scope trace required. A scope capture for the
>> buffered version is here:
>> 4) Emulator is an XDS510-Plus.