Re: [c6x] TI JTAG signal integrity issue

Started by Jeff Brower September 23, 2013
Richard-

Thanks for your reply. The last one, "in the board", was a good guess.

The second one ("knee" glitch in TCK signal) we wrestled with during initial
development of this module 3 years ago. The image in my original post shows an
example of this before and after.

-Jeff

Richard Williams wrote:

> Jeff,
>
> This link may help:
> You probably want to read:
> Advisary EMU_1
>
> and since the root of the problem is probably in the board the DSP is mounted
> to, this link may help:
> R. Williams
>
> ---------- Original Message -----------
> From: "Jeff Brower"
> To: c..., c...
> Sent: Fri, 20 Sep 2013 13:55:02 -0500 (CDT)
> Subject: [c6x] TI JTAG signal integrity issue
>
> > All-
> >
> > I'm posting this question here, the global knowledge source for TI
> > JTAG related issues :-)
> >
> > I have a batch of C5510A modules that are showing inconsistent JTAG
> > scan test results. Out of 6, 3 are passing, two with buffered TCK and
> > RTCK, and 1 without (without = bypass the buffer using zero-ohm Rs).
> > The failing modules also are configured both ways. Due to this
> > variation, I'm concerned that TCK/RTCK isn't the actual problem.
> >
> > My question is how can I verify that JTAG is "trying to work", and
> > thus it might be TCK related? SDConfig doesn't allow this. Is there
> > another utility? Below are some additional notes. Thanks.
> >
> > -Jeff
> >
> > 1) Trace length from JTAG header to C5510A is less than 1".
> >
> > 2) Using dig scope, C5510 clocks are verified (27 MHz). /RESET timing
> > has been verified. Power sequence has been verified. Silicon
> > revision is 2.2, so RST_MODE is ignored.
> >
> > 3) I can post any scope trace required. A scope capture for the
> > buffered version is here:
> >
> > http://signalogic.com/images/Signalogic_C5510_TCK_b4_after_buffer.jpg
> >
> > 4) Emulator is an XDS510-Plus.
> ------- End of Original Message -------