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Hello, I am using the C5502 Device Simulator. In order to perform 32-bit multiplication I am using the DSPLIB function "mul32". I call this assembly function from my C code. According to TI's DSPLIB documentation (spru422h.pdf), each 32-bit multiplication should take 21 cycles with overhead. But, when I used the Profiler in the simulator it showed my close to 80 cycles for this function. Is it possible that the profiler could be incorrect? Has anyone tried profiling this or any similar function on the simulator and got agreeable results? Thanks, Meenakshi. |
C5502 Simulator Profiling
Started by ●January 21, 2005
Reply by ●January 22, 20052005-01-22
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Hi Meenakshi, Check the placement of data, keep data it in internal memory and profile the code. don't sigle step through the code, do it either by range or function profiling. Cheers -Lakshman --- Meenakshi Matai <> wrote: > > Hello, > > I am using the C5502 Device Simulator. In order to > perform 32-bit > multiplication I am using the DSPLIB function > "mul32". > I call this assembly function from my C code. > According to TI's DSPLIB documentation > (spru422h.pdf), each 32-bit > multiplication should take 21 cycles with overhead. > > But, when I used the Profiler in the simulator it > showed my close to 80 > cycles for this function. > > Is it possible that the profiler could be incorrect? > Has anyone tried > profiling this or any similar function on the > simulator and got > agreeable results? > > Thanks, > Meenakshi. > > __________________________________________________ |
Reply by ●January 24, 20052005-01-24
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i don't know that function specifically, however, TI libraries are buggy. you may want to look at the source of that function and optimize it yourself. we have had to do this w/ the I2C CSL functions (they are crap) and the decimation/interpolation functions had problems but i don't remember the specifics. At Friday, 21 January 2005, Meenakshi Matai <> wrote: >Hello, > >I am using the C5502 Device Simulator. In order to perform 32-bit >multiplication I am using the DSPLIB function "mul32". >I call this assembly function from my C code. >According to TI's DSPLIB documentation (spru422h.pdf), each 32-bit >multiplication should take 21 cycles with overhead. > >But, when I used the Profiler in the simulator it showed my close to 80 >cycles for this function. > >Is it possible that the profiler could be incorrect? Has anyone tried >profiling this or any similar function on the simulator and got >agreeable results? > >Thanks, >Meenakshi. > ---------------------------------- Zero Crossings, Inc. -- Embedded and Digital Signal Processing Systems http://www.zerocrossings.com/ |
Reply by ●January 25, 20052005-01-25
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Harland- Gee, I *hope* that their DSPLIB's are not buggy, afterall it contains the most primitive of math operations optimized.In fact they use these kernels and their specs as a form of marketing tool in their respective silicon homepages. So i needn't take a huge leap of faith in expressing my confidence in the dsplib itself(in fact reading the dsplib is one way to understand the best way to code these DSP's!) . The problem as i understand is in verifying the timings expressed by the TI benchmarks.The best way as far as i know to time the DSPLIB functions is to extract the asm code(with no warranty from TI thats the same asm ultimately assembled to create the obj that has been given to you as dsplib!) from the documentation and inline it with my code. And then profile your code. From what i remember their specs dont include function call and return overheads... --Bhooshan On Mon, 24 Jan 2005 08:35:49 -0500, Harland Christofferson <> wrote: > > > i don't know that function specifically, however, TI libraries are > buggy. you may want to look at the source of that function and optimize > it yourself. we have had to do this w/ the I2C CSL functions (they > are crap) and the decimation/interpolation functions had problems > but i don't remember the specifics. > > At Friday, 21 January 2005, Meenakshi Matai <> > wrote: > > >Hello, > > > >I am using the C5502 Device Simulator. In order to perform 32-bit > >multiplication I am using the DSPLIB function "mul32". > >I call this assembly function from my C code. > >According to TI's DSPLIB documentation (spru422h.pdf), each 32-bit > >multiplication should take 21 cycles with overhead. > > > >But, when I used the Profiler in the simulator it showed my close > to 80 > >cycles for this function. > > > >Is it possible that the profiler could be incorrect? Has anyone tried > >profiling this or any similar function on the simulator and got > >agreeable results? > > > >Thanks, > >Meenakshi. > > ---------------------------------- > Zero Crossings, Inc. -- Embedded and Digital Signal Processing Systems > > http://www.zerocrossings.com/ -- --------------------------- "I've missed more than 9000 shots in my career. I've lost almost 300 games. 26 times I've been trusted to take the game winning shot and missed. I've failed over and over again in my life. And that is why I succeed." -- Michael Jordan --------------------------- |
Reply by ●January 25, 20052005-01-25
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Well, by TIs own admission via email and phone conversations, their I2C CSL functions are buggy. Another engineer here had problems w/ interpolation/decimation and had to debug TIs source. We are using TIs DSP/BIOS and I am grateful that this is working .. all software has bugs. I am not saying all of their code is buggy. However, I would not take a leap of faith that their code is perfect ... they are human and overworked like many engineers and they make mistakes too in their releases. At Tuesday, 25 January 2005, Bhooshan Iyer <> wrote: >Harland- >Gee, I *hope* that their DSPLIB's are not buggy, afterall it contains >the most primitive of math operations optimized.In fact they use these >kernels and their specs as a form of marketing tool in their >respective silicon homepages. So i needn't take a huge leap of faith >in expressing my confidence in the dsplib itself(in fact reading the >dsplib is one way to understand the best way to code these DSP's!) . > > The problem as i understand is in verifying the timings expressed by >the TI benchmarks.The best way as far as i know to time the DSPLIB >functions is to extract the asm code(with no warranty from TI thats >the same asm ultimately assembled to create the obj that has been >given to you as dsplib!) from the documentation and inline it with my >code. And then profile your code. From what i remember their specs >dont include function call and return overheads... > >--Bhooshan > >On Mon, 24 Jan 2005 08:35:49 -0500, Harland Christofferson ><> wrote: >> >> >> i don't know that function specifically, however, TI libraries are >> buggy. you may want to look at the source of that function and optimize >> it yourself. we have had to do this w/ the I2C CSL functions (they >> are crap) and the decimation/interpolation functions had problems >> but i don't remember the specifics. >> >> At Friday, 21 January 2005, Meenakshi Matai <> >> wrote: >> >> >Hello, >> > >> >I am using the C5502 Device Simulator. In order to perform 32-bit >> >multiplication I am using the DSPLIB function "mul32". >> >I call this assembly function from my C code. >> >According to TI's DSPLIB documentation (spru422h.pdf), each 32-bit >> >multiplication should take 21 cycles with overhead. >> > >> >But, when I used the Profiler in the simulator it showed my close >> to 80 >> >cycles for this function. >> > >> >Is it possible that the profiler could be incorrect? Has anyone tried >> >profiling this or any similar function on the simulator and got >> >agreeable results? >> > >> >Thanks, >> >Meenakshi. >> > >> >> ---------------------------------- Zero Crossings, Inc. -- Embedded and Digital Signal Processing Systems http://www.zerocrossings.com/ |
Reply by ●January 25, 20052005-01-25
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TI documentation for the 5501/5502 EMIF (SPRU621D) suggests that it is compatable with 64Mbit SDRAM. That would be 2Mx32-bit or 8MB of data. The maximum CE space is only 4MB. So, is it actually possible to interface a 64Mbit SDRAM to a single CE and yet still address all of it? Can a single SDRAM chips span multiple CE's? |
Reply by ●January 25, 20052005-01-25
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Yeah, i also concur that their CSL/BSL( which are more complex and hence moreprone to bugs) are buggy but am not sure about similar conlusions on dsplib-at worst it has few pecularities in terms of conditioning input and output but beyond that i need more evidence to believe that they are buggy. Atleast I can safely say that I have not come across any problems with the few common dsplib functions that i have used in c62x and c55x. On Tue, 25 Jan 2005 08:48:14 -0500, Harland Christofferson <> wrote: > > > Well, by TIs own admission via email and phone conversations, their > I2C CSL functions are buggy. Another engineer here had problems w/ > interpolation/decimation and had to debug TIs source. > > We are using TIs DSP/BIOS and I am grateful that this is working > .. all software has bugs. > > I am not saying all of their code is buggy. However, I would not > take a leap of faith that their code is perfect ... they are human > and overworked like many engineers and they make mistakes too in > their releases. > > At Tuesday, 25 January 2005, Bhooshan Iyer <> > wrote: > > >Harland- > >Gee, I *hope* that their DSPLIB's are not buggy, afterall it contains > >the most primitive of math operations optimized.In fact they use these > >kernels and their specs as a form of marketing tool in their > >respective silicon homepages. So i needn't take a huge leap of faith > >in expressing my confidence in the dsplib itself(in fact reading the > >dsplib is one way to understand the best way to code these DSP's!) . > > > > The problem as i understand is in verifying the timings expressed by > >the TI benchmarks.The best way as far as i know to time the DSPLIB > >functions is to extract the asm code(with no warranty from TI thats > >the same asm ultimately assembled to create the obj that has been > >given to you as dsplib!) from the documentation and inline it with my > >code. And then profile your code. From what i remember their specs > >dont include function call and return overheads... > > > >--Bhooshan > > > >On Mon, 24 Jan 2005 08:35:49 -0500, Harland Christofferson > ><> wrote: > >> > >> > >> i don't know that function specifically, however, TI libraries are > >> buggy. you may want to look at the source of that function and > optimize > >> it yourself. we have had to do this w/ the I2C CSL functions (they > >> are crap) and the decimation/interpolation functions had problems > >> but i don't remember the specifics. > >> > >> At Friday, 21 January 2005, Meenakshi Matai <> > >> wrote: > >> > >> >Hello, > >> > > >> >I am using the C5502 Device Simulator. In order to perform 32-bit > >> >multiplication I am using the DSPLIB function "mul32". > >> >I call this assembly function from my C code. > >> >According to TI's DSPLIB documentation (spru422h.pdf), each 32-bit > >> >multiplication should take 21 cycles with overhead. > >> > > >> >But, when I used the Profiler in the simulator it showed my close > >> to 80 > >> >cycles for this function. > >> > > >> >Is it possible that the profiler could be incorrect? Has anyone > tried > >> >profiling this or any similar function on the simulator and got > >> >agreeable results? > >> > > >> >Thanks, > >> >Meenakshi. > >> > > >> > >> > ---------------------------------- > Zero Crossings, Inc. -- Embedded and Digital Signal Processing Systems > > http://www.zerocrossings.com/ > > -- --------------------------- "I've missed more than 9000 shots in my career. I've lost almost 300 games. 26 times I've been trusted to take the game winning shot and missed. I've failed over and over again in my life. And that is why I succeed." -- Michael Jordan --------------------------- |
Reply by ●January 27, 20052005-01-27
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hi, refer the document spra719. yes, you can connect the 64mbit sdram to a c55x emif. yes, you need to connect more than one CE space. there are some special signals in the emif which you need to use when interfacing to the sdram. the document expalins everything. regards, Dileepan. --- In , Ryan Piwowarski <rpiwowarski@s...> wrote: > > TI documentation for the 5501/5502 EMIF (SPRU621D) suggests that it is > compatable with 64Mbit SDRAM. That would be 2Mx32-bit or 8MB of data. > The maximum CE space is only 4MB. So, is it actually possible to > interface a 64Mbit SDRAM to a single CE and yet still address all of it? > Can a single SDRAM chips span multiple CE's? |
Reply by ●January 27, 20052005-01-27
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Maybe I am misunderstanding your question but you can use a combination of GPIO pins to page through memeory devices that are > 4MB on a a single CEn space. At Tuesday, 25 January 2005, Ryan Piwowarski <rpiwowarski@signalogic. com> wrote: >TI documentation for the 5501/5502 EMIF (SPRU621D) suggests that it is >compatable with 64Mbit SDRAM. That would be 2Mx32-bit or 8MB of data. >The maximum CE space is only 4MB. So, is it actually possible to >interface a 64Mbit SDRAM to a single CE and yet still address all of it? >Can a single SDRAM chips span multiple CE's? > >NEW! You can now post a message or access and search the archives of this group on DSPRelated.com: >http://www.dsprelated.com/groups/c55x/1.php > >____ ---------------------------------- Zero Crossings, Inc. -- Embedded and Digital Signal Processing Systems http://www.zerocrossings.com/ |
Reply by ●January 27, 20052005-01-27
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Dileepan- > refer the document spra719. yes, you can connect the 64mbit sdram to > a c55x emif. yes, you need to connect more than one CE space. there > are some special signals in the emif which you need to use when > interfacing to the sdram. the document expalins everything. Ok, so I see that a 4M x 32 device would use *all* CE spaces... if a designer wanted to leave CE space for SRAM then the largest device usable would be 2M x 32 (64 Mbit). That's cutting it close, because anything less is "past its prime" for mem chip vendors such as Micron Tech, and becoming hard to get. In the future, it might be the case we would procure 4M x 32 chip, but only use half. Arrggh. -Jeff > --- In , Ryan Piwowarski <rpiwowarski@s...> wrote: > > > > TI documentation for the 5501/5502 EMIF (SPRU621D) suggests that it > is > > compatable with 64Mbit SDRAM. That would be 2Mx32-bit or 8MB of > data. > > The maximum CE space is only 4MB. So, is it actually possible to > > interface a 64Mbit SDRAM to a single CE and yet still address all > of it? > > Can a single SDRAM chips span multiple CE's? |
