All,
I'm working with Alex on this project. We've initilized the SDRAM
registers according to the datasheet and to reference designs, and still
nothing. What seems to happen is if you write a value to odd memory locations,
the value sticks and you can read it back. But, ALL odd memory locations show
the same value. This is with the chip in CE1 (which does seem to drop). The chip
is a 256Mb SDRAM from Micron, the MT48LC16M16. It's 16 bits wide. I've
double checked the connections against the 5502 EMIF datasheet (spru621e) and
they're fine. This is definatley a software issue, or damaged hardware.
Does anyone have any code that interfaces to this chip?
-Frankie
5502 EMIF SDRAM
Started by ●July 23, 2005
Reply by ●July 25, 20052005-07-25
Frankie, Alex-
> I'm working with Alex on this project. We've initilized the SDRAM
> registers according to the datasheet and to reference designs, and
> still nothing. What seems to happen is if you write a value to odd
> memory locations, the value sticks and you can read it back.
That sounds kind of close... like it needs a 32-bit interface or something. One
thing I'm wondering... Alex mentioned a 10 MHz input clock I think? Maybe your clock
has to be faster? SDRAM needs refresh right? And refresh has minimum time period
otherwise SDRAM loses its mind...
Other than rate, did you carefully verify SDRAM clk signal? Edges look Ok? No
ringing?
> But, ALL
> odd memory locations show the same value. This is with the chip in
> CE1 (which does seem to drop). The chip is a 256Mb SDRAM from Micron,
> the MT48LC16M16. It's 16 bits wide. I've double checked the
> connections against the 5502 EMIF datasheet (spru621e) and they're
> fine. This is definatley a software issue, or damaged hardware.
One thing to suggest: try setting CE0 up as SRAM, even though the chip is not an
SRAM. SRAM initialization is very simple, right? Almost like an ADC (which is
working on your CE3). Then see if things make sense -- if so the DSP is probably not
damaged.
-Jeff
> I'm working with Alex on this project. We've initilized the SDRAM
> registers according to the datasheet and to reference designs, and
> still nothing. What seems to happen is if you write a value to odd
> memory locations, the value sticks and you can read it back.
That sounds kind of close... like it needs a 32-bit interface or something. One
thing I'm wondering... Alex mentioned a 10 MHz input clock I think? Maybe your clock
has to be faster? SDRAM needs refresh right? And refresh has minimum time period
otherwise SDRAM loses its mind...
Other than rate, did you carefully verify SDRAM clk signal? Edges look Ok? No
ringing?
> But, ALL
> odd memory locations show the same value. This is with the chip in
> CE1 (which does seem to drop). The chip is a 256Mb SDRAM from Micron,
> the MT48LC16M16. It's 16 bits wide. I've double checked the
> connections against the 5502 EMIF datasheet (spru621e) and they're
> fine. This is definatley a software issue, or damaged hardware.
One thing to suggest: try setting CE0 up as SRAM, even though the chip is not an
SRAM. SRAM initialization is very simple, right? Almost like an ADC (which is
working on your CE3). Then see if things make sense -- if so the DSP is probably not
damaged.
-Jeff
