Hello,
I'm doing DMA Transfer on my c5503 System. I have the config as below.
CCR0 is set as:
#define CCR0_VAL DMA_DMACCR_RMK(\
DMA_DMACCR_DSTAMODE_SGLINDX,\
DMA_DMACCR_SRCAMODE_CONST,\
DMA_DMACCR_ENDPROG_OFF,\
DMA_DMACCR_REPEAT_OFF, \
DMA_DMACCR_AUTOINIT_ON,\
DMA_DMACCR_EN_STOP,\
DMA_DMACCR_PRIO_HI,\
DMA_DMACCR_FS_ENABLE,\
DMA_DMACCR_SYNC_NONE\
)
#define CSDP0_VAL DMA_DMACSDP_RMK( \
DMA_DMACSDP_DSTBEN_BURST4,\
DMA_DMACSDP_DSTPACK_ON,\
DMA_DMACSDP_DST_DARAM,\
DMA_DMACSDP_SRCBEN_BURST4,\
DMA_DMACSDP_SRCPACK_ON,\
DMA_DMACSDP_SRC_EMIF,\
DMA_DMACSDP_DATATYPE_16BIT )
Dma runs for word adresses e.g. PTR = 0x0800fd and the source register
is set
DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is coming
only every 2nd read (the [async] read itself comes as it should). Result:
Onyl half the values are read!
If I use cpu acess, the PTR adress can be read in any case properly.
Is it so, that even word adresses won't work? The Dma-spreadsheet says:
"The DMA controller makes 16-bit accesses at the source and at the
destination. The source and destination start addresses must each be
on an even 2-byte boundary; the least significant bit (LSB) must be 0:"
So do they refer to the word or byte adress? In my config odd word adresses
work properly, while even won't do so.
Thanks in advance for your comments
Michael
P.S:
(the config alltogether is:)
DMA_RSET(DMACCR0, CCR0_VAL);
DMA_RSET(DMACSDP0, CSDP0_VAL);
DMA_RSET(DMACEN0, 8);
DMA_RSET(DMACFN0, 1);
DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
DMA_RSET(DMACICR0,CICR_VAL);
// 2*N+1 = 3 Words
DMA_RSET(DMACSEI0, 7);
// programm end
DMA_FSET(DMACCR0, ENDPROG, 1);
// start dma
DMA_FSET(DMACCR0, EN, 1);
DMA - a simple problem
Started by ●January 15, 2006
Reply by ●January 16, 20062006-01-16
Michael-
Is this with external SRAM? If so, do you have Byte Enable signals
connected correctly? We faced problems with even/odd 16-bit access when
we first brought our C5502 board up because of Byte Enable signals not
routed properly.
-Jeff
> I'm doing DMA Transfer on my c5503 System. I have the config as below.
> CCR0 is set as:
> #define CCR0_VAL DMA_DMACCR_RMK(\
> DMA_DMACCR_DSTAMODE_SGLINDX,\
> DMA_DMACCR_SRCAMODE_CONST,\
> DMA_DMACCR_ENDPROG_OFF,\
> DMA_DMACCR_REPEAT_OFF, \
> DMA_DMACCR_AUTOINIT_ON,\
> DMA_DMACCR_EN_STOP,\
> DMA_DMACCR_PRIO_HI,\
> DMA_DMACCR_FS_ENABLE,\
> DMA_DMACCR_SYNC_NONE\
> )
>
> #define CSDP0_VAL DMA_DMACSDP_RMK( \
> DMA_DMACSDP_DSTBEN_BURST4,\
> DMA_DMACSDP_DSTPACK_ON,\
> DMA_DMACSDP_DST_DARAM,\
> DMA_DMACSDP_SRCBEN_BURST4,\
> DMA_DMACSDP_SRCPACK_ON,\
> DMA_DMACSDP_SRC_EMIF,\
> DMA_DMACSDP_DATATYPE_16BIT )
>
> Dma runs for word adresses e.g. PTR = 0x0800fd and the source register
> is set
> DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF); > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> coming
> only every 2nd read (the [async] read itself comes as it should). Result:
> Onyl half the values are read!
>
> If I use cpu acess, the PTR adress can be read in any case properly.
>
> Is it so, that even word adresses won't work? The Dma-spreadsheet says:
> "The DMA controller makes 16-bit accesses at the source and at the
> destination. The source and destination start addresses must each be
> on an even 2-byte boundary; the least significant bit (LSB) must be 0:"
>
> So do they refer to the word or byte adress? In my config odd word
> adresses
> work properly, while even won't do so.
>
> Thanks in advance for your comments
>
> Michael
> P.S:
> (the config alltogether is:)
> DMA_RSET(DMACCR0, CCR0_VAL);
> DMA_RSET(DMACSDP0, CSDP0_VAL);
> DMA_RSET(DMACEN0, 8);
> DMA_RSET(DMACFN0, 1);
> DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> DMA_RSET(DMACICR0,CICR_VAL);
> // 2*N+1 = 3 Words
> DMA_RSET(DMACSEI0, 7);
> // programm end
> DMA_FSET(DMACCR0, ENDPROG, 1);
> // start dma
> DMA_FSET(DMACCR0, EN, 1); >
Is this with external SRAM? If so, do you have Byte Enable signals
connected correctly? We faced problems with even/odd 16-bit access when
we first brought our C5502 board up because of Byte Enable signals not
routed properly.
-Jeff
> I'm doing DMA Transfer on my c5503 System. I have the config as below.
> CCR0 is set as:
> #define CCR0_VAL DMA_DMACCR_RMK(\
> DMA_DMACCR_DSTAMODE_SGLINDX,\
> DMA_DMACCR_SRCAMODE_CONST,\
> DMA_DMACCR_ENDPROG_OFF,\
> DMA_DMACCR_REPEAT_OFF, \
> DMA_DMACCR_AUTOINIT_ON,\
> DMA_DMACCR_EN_STOP,\
> DMA_DMACCR_PRIO_HI,\
> DMA_DMACCR_FS_ENABLE,\
> DMA_DMACCR_SYNC_NONE\
> )
>
> #define CSDP0_VAL DMA_DMACSDP_RMK( \
> DMA_DMACSDP_DSTBEN_BURST4,\
> DMA_DMACSDP_DSTPACK_ON,\
> DMA_DMACSDP_DST_DARAM,\
> DMA_DMACSDP_SRCBEN_BURST4,\
> DMA_DMACSDP_SRCPACK_ON,\
> DMA_DMACSDP_SRC_EMIF,\
> DMA_DMACSDP_DATATYPE_16BIT )
>
> Dma runs for word adresses e.g. PTR = 0x0800fd and the source register
> is set
> DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF); > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> coming
> only every 2nd read (the [async] read itself comes as it should). Result:
> Onyl half the values are read!
>
> If I use cpu acess, the PTR adress can be read in any case properly.
>
> Is it so, that even word adresses won't work? The Dma-spreadsheet says:
> "The DMA controller makes 16-bit accesses at the source and at the
> destination. The source and destination start addresses must each be
> on an even 2-byte boundary; the least significant bit (LSB) must be 0:"
>
> So do they refer to the word or byte adress? In my config odd word
> adresses
> work properly, while even won't do so.
>
> Thanks in advance for your comments
>
> Michael
> P.S:
> (the config alltogether is:)
> DMA_RSET(DMACCR0, CCR0_VAL);
> DMA_RSET(DMACSDP0, CSDP0_VAL);
> DMA_RSET(DMACEN0, 8);
> DMA_RSET(DMACFN0, 1);
> DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> DMA_RSET(DMACICR0,CICR_VAL);
> // 2*N+1 = 3 Words
> DMA_RSET(DMACSEI0, 7);
> // programm end
> DMA_FSET(DMACCR0, ENDPROG, 1);
> // start dma
> DMA_FSET(DMACCR0, EN, 1); >
Reply by ●January 16, 20062006-01-16
Hi Michael,
This feature of C55x is known as packing/unpacking on
the fly; DMA can pack or unpack the data...If you pass
odd address (0x0800fe) as destination address, the
values at destination address are unpacked...means a
16-bit memory will have a byte data.
Best Regards,
-Lakshman
--- Jeff Brower <jbrower@jbro...> wrote:
> Michael-
>
> Is this with external SRAM? If so, do you have Byte
> Enable signals
> connected correctly? We faced problems with
> even/odd 16-bit access when
> we first brought our C5502 board up because of Byte
> Enable signals not
> routed properly.
>
> -Jeff
>
> > I'm doing DMA Transfer on my c5503 System. I have
> the config as below.
> > CCR0 is set as:
> > #define CCR0_VAL DMA_DMACCR_RMK(\
> > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > DMA_DMACCR_SRCAMODE_CONST,\
> > DMA_DMACCR_ENDPROG_OFF,\
> > DMA_DMACCR_REPEAT_OFF, \
> > DMA_DMACCR_AUTOINIT_ON,\
> > DMA_DMACCR_EN_STOP,\
> > DMA_DMACCR_PRIO_HI,\
> > DMA_DMACCR_FS_ENABLE,\
> > DMA_DMACCR_SYNC_NONE\
> > )
> >
> > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > DMA_DMACSDP_DSTBEN_BURST4,\
> > DMA_DMACSDP_DSTPACK_ON,\
> > DMA_DMACSDP_DST_DARAM,\
> > DMA_DMACSDP_SRCBEN_BURST4,\
> > DMA_DMACSDP_SRCPACK_ON,\
> > DMA_DMACSDP_SRC_EMIF,\
> > DMA_DMACSDP_DATATYPE_16BIT )
> >
> > Dma runs for word adresses e.g. PTR = 0x0800fd and
> the source register
> > is set
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> >
> >
> > My problem: If I use PTR 0x0800fe the chip enable
> (ce0 in my case) is
> > coming
> > only every 2nd read (the [async] read itself comes
> as it should). Result:
> > Onyl half the values are read!
> >
> > If I use cpu acess, the PTR adress can be read in
> any case properly.
> >
> > Is it so, that even word adresses won't work? The
> Dma-spreadsheet says:
> > "The DMA controller makes 16-bit accesses at the
> source and at the
> > destination. The source and destination start
> addresses must each be
> > on an even 2-byte boundary; the least significant
> bit (LSB) must be 0:"
> >
> > So do they refer to the word or byte adress? In my
> config odd word
> > adresses
> > work properly, while even won't do so.
> >
> > Thanks in advance for your comments
> >
> > Michael
> > P.S:
> > (the config alltogether is:)
> > DMA_RSET(DMACCR0, CCR0_VAL);
> > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > DMA_RSET(DMACEN0, 8);
> > DMA_RSET(DMACFN0, 1);
> > DMA_RSET(DMACDSAL0, (((Uint32)
> DMA_1_PTR)<<1)&0xFFFF);
> > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)&
> 0xFFFF);
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACICR0,CICR_VAL);
> > // 2*N+1 = 3 Words
> > DMA_RSET(DMACSEI0, 7);
> > // programm end
> > DMA_FSET(DMACCR0, ENDPROG, 1);
> > // start dma
> > DMA_FSET(DMACCR0, EN, 1);
This feature of C55x is known as packing/unpacking on
the fly; DMA can pack or unpack the data...If you pass
odd address (0x0800fe) as destination address, the
values at destination address are unpacked...means a
16-bit memory will have a byte data.
Best Regards,
-Lakshman
--- Jeff Brower <jbrower@jbro...> wrote:
> Michael-
>
> Is this with external SRAM? If so, do you have Byte
> Enable signals
> connected correctly? We faced problems with
> even/odd 16-bit access when
> we first brought our C5502 board up because of Byte
> Enable signals not
> routed properly.
>
> -Jeff
>
> > I'm doing DMA Transfer on my c5503 System. I have
> the config as below.
> > CCR0 is set as:
> > #define CCR0_VAL DMA_DMACCR_RMK(\
> > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > DMA_DMACCR_SRCAMODE_CONST,\
> > DMA_DMACCR_ENDPROG_OFF,\
> > DMA_DMACCR_REPEAT_OFF, \
> > DMA_DMACCR_AUTOINIT_ON,\
> > DMA_DMACCR_EN_STOP,\
> > DMA_DMACCR_PRIO_HI,\
> > DMA_DMACCR_FS_ENABLE,\
> > DMA_DMACCR_SYNC_NONE\
> > )
> >
> > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > DMA_DMACSDP_DSTBEN_BURST4,\
> > DMA_DMACSDP_DSTPACK_ON,\
> > DMA_DMACSDP_DST_DARAM,\
> > DMA_DMACSDP_SRCBEN_BURST4,\
> > DMA_DMACSDP_SRCPACK_ON,\
> > DMA_DMACSDP_SRC_EMIF,\
> > DMA_DMACSDP_DATATYPE_16BIT )
> >
> > Dma runs for word adresses e.g. PTR = 0x0800fd and
> the source register
> > is set
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> >
> >
> > My problem: If I use PTR 0x0800fe the chip enable
> (ce0 in my case) is
> > coming
> > only every 2nd read (the [async] read itself comes
> as it should). Result:
> > Onyl half the values are read!
> >
> > If I use cpu acess, the PTR adress can be read in
> any case properly.
> >
> > Is it so, that even word adresses won't work? The
> Dma-spreadsheet says:
> > "The DMA controller makes 16-bit accesses at the
> source and at the
> > destination. The source and destination start
> addresses must each be
> > on an even 2-byte boundary; the least significant
> bit (LSB) must be 0:"
> >
> > So do they refer to the word or byte adress? In my
> config odd word
> > adresses
> > work properly, while even won't do so.
> >
> > Thanks in advance for your comments
> >
> > Michael
> > P.S:
> > (the config alltogether is:)
> > DMA_RSET(DMACCR0, CCR0_VAL);
> > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > DMA_RSET(DMACEN0, 8);
> > DMA_RSET(DMACFN0, 1);
> > DMA_RSET(DMACDSAL0, (((Uint32)
> DMA_1_PTR)<<1)&0xFFFF);
> > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)&
> 0xFFFF);
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACICR0,CICR_VAL);
> > // 2*N+1 = 3 Words
> > DMA_RSET(DMACSEI0, 7);
> > // programm end
> > DMA_FSET(DMACCR0, ENDPROG, 1);
> > // start dma
> > DMA_FSET(DMACCR0, EN, 1);
Reply by ●January 16, 20062006-01-16
Jeff,
no this is an external async interface. Also direct cpu acess works, but not
dma!
Michael
Am Montag, 16. Januar 2006 14:14 schrieb Jeff Brower:
> Michael-
>
> Is this with external SRAM? If so, do you have Byte Enable signals
> connected correctly? We faced problems with even/odd 16-bit access when
> we first brought our C5502 board up because of Byte Enable signals not
> routed properly.
>
> -Jeff
>
> > I'm doing DMA Transfer on my c5503 System. I have the config as below.
> > CCR0 is set as:
> > #define CCR0_VAL DMA_DMACCR_RMK(\
> > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > DMA_DMACCR_SRCAMODE_CONST,\
> > DMA_DMACCR_ENDPROG_OFF,\
> > DMA_DMACCR_REPEAT_OFF, \
> > DMA_DMACCR_AUTOINIT_ON,\
> > DMA_DMACCR_EN_STOP,\
> > DMA_DMACCR_PRIO_HI,\
> > DMA_DMACCR_FS_ENABLE,\
> > DMA_DMACCR_SYNC_NONE\
> > )
> >
> > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > DMA_DMACSDP_DSTBEN_BURST4,\
> > DMA_DMACSDP_DSTPACK_ON,\
> > DMA_DMACSDP_DST_DARAM,\
> > DMA_DMACSDP_SRCBEN_BURST4,\
> > DMA_DMACSDP_SRCPACK_ON,\
> > DMA_DMACSDP_SRC_EMIF,\
> > DMA_DMACSDP_DATATYPE_16BIT )
> >
> > Dma runs for word adresses e.g. PTR = 0x0800fd and the source register
> > is set
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> >
> >
> > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> > coming
> > only every 2nd read (the [async] read itself comes as it should). Result:
> > Onyl half the values are read!
> >
> > If I use cpu acess, the PTR adress can be read in any case properly.
> >
> > Is it so, that even word adresses won't work? The Dma-spreadsheet says:
> > "The DMA controller makes 16-bit accesses at the source and at the
> > destination. The source and destination start addresses must each be
> > on an even 2-byte boundary; the least significant bit (LSB) must be 0:"
> >
> > So do they refer to the word or byte adress? In my config odd word
> > adresses
> > work properly, while even won't do so.
> >
> > Thanks in advance for your comments
> >
> > Michael
> > P.S:
> > (the config alltogether is:)
> > DMA_RSET(DMACCR0, CCR0_VAL);
> > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > DMA_RSET(DMACEN0, 8);
> > DMA_RSET(DMACFN0, 1);
> > DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACICR0,CICR_VAL);
> > // 2*N+1 = 3 Words
> > DMA_RSET(DMACSEI0, 7);
> > // programm end
> > DMA_FSET(DMACCR0, ENDPROG, 1);
> > // start dma
> > DMA_FSET(DMACCR0, EN, 1);
> >
no this is an external async interface. Also direct cpu acess works, but not
dma!
Michael
Am Montag, 16. Januar 2006 14:14 schrieb Jeff Brower:
> Michael-
>
> Is this with external SRAM? If so, do you have Byte Enable signals
> connected correctly? We faced problems with even/odd 16-bit access when
> we first brought our C5502 board up because of Byte Enable signals not
> routed properly.
>
> -Jeff
>
> > I'm doing DMA Transfer on my c5503 System. I have the config as below.
> > CCR0 is set as:
> > #define CCR0_VAL DMA_DMACCR_RMK(\
> > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > DMA_DMACCR_SRCAMODE_CONST,\
> > DMA_DMACCR_ENDPROG_OFF,\
> > DMA_DMACCR_REPEAT_OFF, \
> > DMA_DMACCR_AUTOINIT_ON,\
> > DMA_DMACCR_EN_STOP,\
> > DMA_DMACCR_PRIO_HI,\
> > DMA_DMACCR_FS_ENABLE,\
> > DMA_DMACCR_SYNC_NONE\
> > )
> >
> > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > DMA_DMACSDP_DSTBEN_BURST4,\
> > DMA_DMACSDP_DSTPACK_ON,\
> > DMA_DMACSDP_DST_DARAM,\
> > DMA_DMACSDP_SRCBEN_BURST4,\
> > DMA_DMACSDP_SRCPACK_ON,\
> > DMA_DMACSDP_SRC_EMIF,\
> > DMA_DMACSDP_DATATYPE_16BIT )
> >
> > Dma runs for word adresses e.g. PTR = 0x0800fd and the source register
> > is set
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> >
> >
> > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> > coming
> > only every 2nd read (the [async] read itself comes as it should). Result:
> > Onyl half the values are read!
> >
> > If I use cpu acess, the PTR adress can be read in any case properly.
> >
> > Is it so, that even word adresses won't work? The Dma-spreadsheet says:
> > "The DMA controller makes 16-bit accesses at the source and at the
> > destination. The source and destination start addresses must each be
> > on an even 2-byte boundary; the least significant bit (LSB) must be 0:"
> >
> > So do they refer to the word or byte adress? In my config odd word
> > adresses
> > work properly, while even won't do so.
> >
> > Thanks in advance for your comments
> >
> > Michael
> > P.S:
> > (the config alltogether is:)
> > DMA_RSET(DMACCR0, CCR0_VAL);
> > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > DMA_RSET(DMACEN0, 8);
> > DMA_RSET(DMACFN0, 1);
> > DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACICR0,CICR_VAL);
> > // 2*N+1 = 3 Words
> > DMA_RSET(DMACSEI0, 7);
> > // programm end
> > DMA_FSET(DMACCR0, ENDPROG, 1);
> > // start dma
> > DMA_FSET(DMACCR0, EN, 1);
> >
Reply by ●January 16, 20062006-01-16
Jeff,
to be even more correct: Its a 16 bit Async-Interface. Byte Enable is not
needed and therefore not connected to the Chip. But it seems, as if the DMA
does make a 8Bit access or is somehow disturbed...
Michael Michael
Am Montag, 16. Januar 2006 14:14 schrieb Jeff Brower:
> Michael-
>
> Is this with external SRAM? If so, do you have Byte Enable signals
> connected correctly? We faced problems with even/odd 16-bit access when
> we first brought our C5502 board up because of Byte Enable signals not
> routed properly.
>
> -Jeff
>
> > I'm doing DMA Transfer on my c5503 System. I have the config as below.
> > CCR0 is set as:
> > #define CCR0_VAL DMA_DMACCR_RMK(\
> > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > DMA_DMACCR_SRCAMODE_CONST,\
> > DMA_DMACCR_ENDPROG_OFF,\
> > DMA_DMACCR_REPEAT_OFF, \
> > DMA_DMACCR_AUTOINIT_ON,\
> > DMA_DMACCR_EN_STOP,\
> > DMA_DMACCR_PRIO_HI,\
> > DMA_DMACCR_FS_ENABLE,\
> > DMA_DMACCR_SYNC_NONE\
> > )
> >
> > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > DMA_DMACSDP_DSTBEN_BURST4,\
> > DMA_DMACSDP_DSTPACK_ON,\
> > DMA_DMACSDP_DST_DARAM,\
> > DMA_DMACSDP_SRCBEN_BURST4,\
> > DMA_DMACSDP_SRCPACK_ON,\
> > DMA_DMACSDP_SRC_EMIF,\
> > DMA_DMACSDP_DATATYPE_16BIT )
> >
> > Dma runs for word adresses e.g. PTR = 0x0800fd and the source register
> > is set
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> >
> >
> > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> > coming
> > only every 2nd read (the [async] read itself comes as it should). Result:
> > Onyl half the values are read!
> >
> > If I use cpu acess, the PTR adress can be read in any case properly.
> >
> > Is it so, that even word adresses won't work? The Dma-spreadsheet says:
> > "The DMA controller makes 16-bit accesses at the source and at the
> > destination. The source and destination start addresses must each be
> > on an even 2-byte boundary; the least significant bit (LSB) must be 0:"
> >
> > So do they refer to the word or byte adress? In my config odd word
> > adresses
> > work properly, while even won't do so.
> >
> > Thanks in advance for your comments
> >
> > Michael
> > P.S:
> > (the config alltogether is:)
> > DMA_RSET(DMACCR0, CCR0_VAL);
> > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > DMA_RSET(DMACEN0, 8);
> > DMA_RSET(DMACFN0, 1);
> > DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACICR0,CICR_VAL);
> > // 2*N+1 = 3 Words
> > DMA_RSET(DMACSEI0, 7);
> > // programm end
> > DMA_FSET(DMACCR0, ENDPROG, 1);
> > // start dma
> > DMA_FSET(DMACCR0, EN, 1);
> >
to be even more correct: Its a 16 bit Async-Interface. Byte Enable is not
needed and therefore not connected to the Chip. But it seems, as if the DMA
does make a 8Bit access or is somehow disturbed...
Michael Michael
Am Montag, 16. Januar 2006 14:14 schrieb Jeff Brower:
> Michael-
>
> Is this with external SRAM? If so, do you have Byte Enable signals
> connected correctly? We faced problems with even/odd 16-bit access when
> we first brought our C5502 board up because of Byte Enable signals not
> routed properly.
>
> -Jeff
>
> > I'm doing DMA Transfer on my c5503 System. I have the config as below.
> > CCR0 is set as:
> > #define CCR0_VAL DMA_DMACCR_RMK(\
> > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > DMA_DMACCR_SRCAMODE_CONST,\
> > DMA_DMACCR_ENDPROG_OFF,\
> > DMA_DMACCR_REPEAT_OFF, \
> > DMA_DMACCR_AUTOINIT_ON,\
> > DMA_DMACCR_EN_STOP,\
> > DMA_DMACCR_PRIO_HI,\
> > DMA_DMACCR_FS_ENABLE,\
> > DMA_DMACCR_SYNC_NONE\
> > )
> >
> > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > DMA_DMACSDP_DSTBEN_BURST4,\
> > DMA_DMACSDP_DSTPACK_ON,\
> > DMA_DMACSDP_DST_DARAM,\
> > DMA_DMACSDP_SRCBEN_BURST4,\
> > DMA_DMACSDP_SRCPACK_ON,\
> > DMA_DMACSDP_SRC_EMIF,\
> > DMA_DMACSDP_DATATYPE_16BIT )
> >
> > Dma runs for word adresses e.g. PTR = 0x0800fd and the source register
> > is set
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> >
> >
> > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> > coming
> > only every 2nd read (the [async] read itself comes as it should). Result:
> > Onyl half the values are read!
> >
> > If I use cpu acess, the PTR adress can be read in any case properly.
> >
> > Is it so, that even word adresses won't work? The Dma-spreadsheet says:
> > "The DMA controller makes 16-bit accesses at the source and at the
> > destination. The source and destination start addresses must each be
> > on an even 2-byte boundary; the least significant bit (LSB) must be 0:"
> >
> > So do they refer to the word or byte adress? In my config odd word
> > adresses
> > work properly, while even won't do so.
> >
> > Thanks in advance for your comments
> >
> > Michael
> > P.S:
> > (the config alltogether is:)
> > DMA_RSET(DMACCR0, CCR0_VAL);
> > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > DMA_RSET(DMACEN0, 8);
> > DMA_RSET(DMACFN0, 1);
> > DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > DMA_RSET(DMACICR0,CICR_VAL);
> > // 2*N+1 = 3 Words
> > DMA_RSET(DMACSEI0, 7);
> > // programm end
> > DMA_FSET(DMACCR0, ENDPROG, 1);
> > // start dma
> > DMA_FSET(DMACCR0, EN, 1);
> >
Reply by ●January 16, 20062006-01-16
Michael-
> to be even more correct: Its a 16 bit Async-Interface. Byte Enable is not
> needed and therefore not connected to the Chip. But it seems, as if the DMA
> does make a 8Bit access or is somehow disturbed...
The C5502 *only* makes 32-bit accesses, no matter what the instruction or chip
operation. We have memory width set to 16 (2x 16-bit wide devices), so byte enables
are needed on 16-bit writes because one half of the data (either upper or lower) is
"don't care" and one of the SRAMs should not be enabled.
This only applies to external SRAM. I don't know if the C5503 works the same way,
but would imagine it does.
-Jeff
> Am Montag, 16. Januar 2006 14:14 schrieb Jeff Brower:
> > Michael-
> >
> > Is this with external SRAM? If so, do you have Byte Enable signals
> > connected correctly? We faced problems with even/odd 16-bit access when
> > we first brought our C5502 board up because of Byte Enable signals not
> > routed properly.
> >
> > -Jeff
> >
> > > I'm doing DMA Transfer on my c5503 System. I have the config as below.
> > > CCR0 is set as:
> > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > DMA_DMACCR_SRCAMODE_CONST,\
> > > DMA_DMACCR_ENDPROG_OFF,\
> > > DMA_DMACCR_REPEAT_OFF, \
> > > DMA_DMACCR_AUTOINIT_ON,\
> > > DMA_DMACCR_EN_STOP,\
> > > DMA_DMACCR_PRIO_HI,\
> > > DMA_DMACCR_FS_ENABLE,\
> > > DMA_DMACCR_SYNC_NONE\
> > > )
> > >
> > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > DMA_DMACSDP_DSTPACK_ON,\
> > > DMA_DMACSDP_DST_DARAM,\
> > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > DMA_DMACSDP_SRCPACK_ON,\
> > > DMA_DMACSDP_SRC_EMIF,\
> > > DMA_DMACSDP_DATATYPE_16BIT )
> > >
> > > Dma runs for word adresses e.g. PTR = 0x0800fd and the source register
> > > is set
> > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > >
> > >
> > > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> > > coming
> > > only every 2nd read (the [async] read itself comes as it should). Result:
> > > Onyl half the values are read!
> > >
> > > If I use cpu acess, the PTR adress can be read in any case properly.
> > >
> > > Is it so, that even word adresses won't work? The Dma-spreadsheet says:
> > > "The DMA controller makes 16-bit accesses at the source and at the
> > > destination. The source and destination start addresses must each be
> > > on an even 2-byte boundary; the least significant bit (LSB) must be 0:"
> > >
> > > So do they refer to the word or byte adress? In my config odd word
> > > adresses
> > > work properly, while even won't do so.
> > >
> > > Thanks in advance for your comments
> > >
> > > Michael
> > > P.S:
> > > (the config alltogether is:)
> > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > DMA_RSET(DMACEN0, 8);
> > > DMA_RSET(DMACFN0, 1);
> > > DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> > > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > > DMA_RSET(DMACICR0,CICR_VAL);
> > > // 2*N+1 = 3 Words
> > > DMA_RSET(DMACSEI0, 7);
> > > // programm end
> > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > // start dma
> > > DMA_FSET(DMACCR0, EN, 1);
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> to be even more correct: Its a 16 bit Async-Interface. Byte Enable is not
> needed and therefore not connected to the Chip. But it seems, as if the DMA
> does make a 8Bit access or is somehow disturbed...
The C5502 *only* makes 32-bit accesses, no matter what the instruction or chip
operation. We have memory width set to 16 (2x 16-bit wide devices), so byte enables
are needed on 16-bit writes because one half of the data (either upper or lower) is
"don't care" and one of the SRAMs should not be enabled.
This only applies to external SRAM. I don't know if the C5503 works the same way,
but would imagine it does.
-Jeff
> Am Montag, 16. Januar 2006 14:14 schrieb Jeff Brower:
> > Michael-
> >
> > Is this with external SRAM? If so, do you have Byte Enable signals
> > connected correctly? We faced problems with even/odd 16-bit access when
> > we first brought our C5502 board up because of Byte Enable signals not
> > routed properly.
> >
> > -Jeff
> >
> > > I'm doing DMA Transfer on my c5503 System. I have the config as below.
> > > CCR0 is set as:
> > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > DMA_DMACCR_SRCAMODE_CONST,\
> > > DMA_DMACCR_ENDPROG_OFF,\
> > > DMA_DMACCR_REPEAT_OFF, \
> > > DMA_DMACCR_AUTOINIT_ON,\
> > > DMA_DMACCR_EN_STOP,\
> > > DMA_DMACCR_PRIO_HI,\
> > > DMA_DMACCR_FS_ENABLE,\
> > > DMA_DMACCR_SYNC_NONE\
> > > )
> > >
> > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > DMA_DMACSDP_DSTPACK_ON,\
> > > DMA_DMACSDP_DST_DARAM,\
> > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > DMA_DMACSDP_SRCPACK_ON,\
> > > DMA_DMACSDP_SRC_EMIF,\
> > > DMA_DMACSDP_DATATYPE_16BIT )
> > >
> > > Dma runs for word adresses e.g. PTR = 0x0800fd and the source register
> > > is set
> > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > >
> > >
> > > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> > > coming
> > > only every 2nd read (the [async] read itself comes as it should). Result:
> > > Onyl half the values are read!
> > >
> > > If I use cpu acess, the PTR adress can be read in any case properly.
> > >
> > > Is it so, that even word adresses won't work? The Dma-spreadsheet says:
> > > "The DMA controller makes 16-bit accesses at the source and at the
> > > destination. The source and destination start addresses must each be
> > > on an even 2-byte boundary; the least significant bit (LSB) must be 0:"
> > >
> > > So do they refer to the word or byte adress? In my config odd word
> > > adresses
> > > work properly, while even won't do so.
> > >
> > > Thanks in advance for your comments
> > >
> > > Michael
> > > P.S:
> > > (the config alltogether is:)
> > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > DMA_RSET(DMACEN0, 8);
> > > DMA_RSET(DMACFN0, 1);
> > > DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> > > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > > DMA_RSET(DMACICR0,CICR_VAL);
> > > // 2*N+1 = 3 Words
> > > DMA_RSET(DMACSEI0, 7);
> > > // programm end
> > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > // start dma
> > > DMA_FSET(DMACCR0, EN, 1);
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
Reply by ●January 17, 20062006-01-17
Jeff,
Hm, the c5503 has an emif which can be configured as async 8 (read only) or 16
bit. DMA can be configured as 8,16,32 bit. We did configure 16 bit for emif
and DMA, the byte enable should have influence therefore. (CPU acess will be
only 16 bit in our case)
Again, the strange thing is, dma does not work as expected in our case, if we
read several times from an even word adress. Odd word adresses work as
expected.
Anyway only
Am Montag, 16. Januar 2006 17:57 schrieben Sie:
> The C5502 *only* makes 32-bit accesses, no matter what the instruction or
> chip operation. We have memory width set to 16 (2x 16-bit wide devices),
> so byte enables are needed on 16-bit writes because one half of the data
> (either upper or lower) is "don't care" and one of the SRAMs should not be
> enabled.
>
> This only applies to external SRAM. I don't know if the C5503 works the
> same way, but would imagine it does.
>
> -Jeff
>
> > Am Montag, 16. Januar 2006 14:14 schrieb Jeff Brower:
> > > Michael-
> > >
> > > Is this with external SRAM? If so, do you have Byte Enable signals
> > > connected correctly? We faced problems with even/odd 16-bit access
> > > when we first brought our C5502 board up because of Byte Enable signals
> > > not routed properly.
> > >
> > > -Jeff
> > >
> > > > I'm doing DMA Transfer on my c5503 System. I have the config as
> > > > below. CCR0 is set as:
> > > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > > DMA_DMACCR_SRCAMODE_CONST,\
> > > > DMA_DMACCR_ENDPROG_OFF,\
> > > > DMA_DMACCR_REPEAT_OFF, \
> > > > DMA_DMACCR_AUTOINIT_ON,\
> > > > DMA_DMACCR_EN_STOP,\
> > > > DMA_DMACCR_PRIO_HI,\
> > > > DMA_DMACCR_FS_ENABLE,\
> > > > DMA_DMACCR_SYNC_NONE\
> > > > )
> > > >
> > > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > > DMA_DMACSDP_DSTPACK_ON,\
> > > > DMA_DMACSDP_DST_DARAM,\
> > > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > > DMA_DMACSDP_SRCPACK_ON,\
> > > > DMA_DMACSDP_SRC_EMIF,\
> > > > DMA_DMACSDP_DATATYPE_16BIT )
> > > >
> > > > Dma runs for word adresses e.g. PTR = 0x0800fd and the source
> > > > register is set
> > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > > >
> > > >
> > > > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> > > > coming
> > > > only every 2nd read (the [async] read itself comes as it should).
> > > > Result: Onyl half the values are read!
> > > >
> > > > If I use cpu acess, the PTR adress can be read in any case properly.
> > > >
> > > > Is it so, that even word adresses won't work? The Dma-spreadsheet
> > > > says: "The DMA controller makes 16-bit accesses at the source and at
> > > > the destination. The source and destination start addresses must each
> > > > be on an even 2-byte boundary; the least significant bit (LSB) must
> > > > be 0:"
> > > >
> > > > So do they refer to the word or byte adress? In my config odd word
> > > > adresses
> > > > work properly, while even won't do so.
> > > >
> > > > Thanks in advance for your comments
> > > >
> > > > Michael
> > > > P.S:
> > > > (the config alltogether is:)
> > > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > > DMA_RSET(DMACEN0, 8);
> > > > DMA_RSET(DMACFN0, 1);
> > > > DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> > > > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > > > DMA_RSET(DMACICR0,CICR_VAL);
> > > > // 2*N+1 = 3 Words
> > > > DMA_RSET(DMACSEI0, 7);
> > > > // programm end
> > > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > > // start dma
> > > > DMA_FSET(DMACCR0, EN, 1);
> > > >
Hm, the c5503 has an emif which can be configured as async 8 (read only) or 16
bit. DMA can be configured as 8,16,32 bit. We did configure 16 bit for emif
and DMA, the byte enable should have influence therefore. (CPU acess will be
only 16 bit in our case)
Again, the strange thing is, dma does not work as expected in our case, if we
read several times from an even word adress. Odd word adresses work as
expected.
Anyway only
Am Montag, 16. Januar 2006 17:57 schrieben Sie:
> The C5502 *only* makes 32-bit accesses, no matter what the instruction or
> chip operation. We have memory width set to 16 (2x 16-bit wide devices),
> so byte enables are needed on 16-bit writes because one half of the data
> (either upper or lower) is "don't care" and one of the SRAMs should not be
> enabled.
>
> This only applies to external SRAM. I don't know if the C5503 works the
> same way, but would imagine it does.
>
> -Jeff
>
> > Am Montag, 16. Januar 2006 14:14 schrieb Jeff Brower:
> > > Michael-
> > >
> > > Is this with external SRAM? If so, do you have Byte Enable signals
> > > connected correctly? We faced problems with even/odd 16-bit access
> > > when we first brought our C5502 board up because of Byte Enable signals
> > > not routed properly.
> > >
> > > -Jeff
> > >
> > > > I'm doing DMA Transfer on my c5503 System. I have the config as
> > > > below. CCR0 is set as:
> > > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > > DMA_DMACCR_SRCAMODE_CONST,\
> > > > DMA_DMACCR_ENDPROG_OFF,\
> > > > DMA_DMACCR_REPEAT_OFF, \
> > > > DMA_DMACCR_AUTOINIT_ON,\
> > > > DMA_DMACCR_EN_STOP,\
> > > > DMA_DMACCR_PRIO_HI,\
> > > > DMA_DMACCR_FS_ENABLE,\
> > > > DMA_DMACCR_SYNC_NONE\
> > > > )
> > > >
> > > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > > DMA_DMACSDP_DSTPACK_ON,\
> > > > DMA_DMACSDP_DST_DARAM,\
> > > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > > DMA_DMACSDP_SRCPACK_ON,\
> > > > DMA_DMACSDP_SRC_EMIF,\
> > > > DMA_DMACSDP_DATATYPE_16BIT )
> > > >
> > > > Dma runs for word adresses e.g. PTR = 0x0800fd and the source
> > > > register is set
> > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > > >
> > > >
> > > > My problem: If I use PTR 0x0800fe the chip enable (ce0 in my case) is
> > > > coming
> > > > only every 2nd read (the [async] read itself comes as it should).
> > > > Result: Onyl half the values are read!
> > > >
> > > > If I use cpu acess, the PTR adress can be read in any case properly.
> > > >
> > > > Is it so, that even word adresses won't work? The Dma-spreadsheet
> > > > says: "The DMA controller makes 16-bit accesses at the source and at
> > > > the destination. The source and destination start addresses must each
> > > > be on an even 2-byte boundary; the least significant bit (LSB) must
> > > > be 0:"
> > > >
> > > > So do they refer to the word or byte adress? In my config odd word
> > > > adresses
> > > > work properly, while even won't do so.
> > > >
> > > > Thanks in advance for your comments
> > > >
> > > > Michael
> > > > P.S:
> > > > (the config alltogether is:)
> > > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > > DMA_RSET(DMACEN0, 8);
> > > > DMA_RSET(DMACFN0, 1);
> > > > DMA_RSET(DMACDSAL0, (((Uint32) DMA_1_PTR)<<1)&0xFFFF);
> > > > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)& 0xFFFF);
> > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > > > DMA_RSET(DMACICR0,CICR_VAL);
> > > > // 2*N+1 = 3 Words
> > > > DMA_RSET(DMACSEI0, 7);
> > > > // programm end
> > > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > > // start dma
> > > > DMA_FSET(DMACCR0, EN, 1);
> > > >
Reply by ●January 17, 20062006-01-17
Hi Lakshma,
0x0800fe is word adress and its the source adress.
Also it's shifted left, so there should be no difference between 0x800fe and
0x800fd refering to odd or even (or do I misunderstand something?)
Michael
Am Montag, 16. Januar 2006 15:36 schrieb Lakshman:
> Hi Michael,
>
> This feature of C55x is known as packing/unpacking on
> the fly; DMA can pack or unpack the data...If you pass
> odd address (0x0800fe) as destination address, the
> values at destination address are unpacked...means a
> 16-bit memory will have a byte data.
>
> Best Regards,
> -Lakshman
>
> --- Jeff Brower <jbrower@jbro...> wrote:
> > Michael-
> >
> > Is this with external SRAM? If so, do you have Byte
> > Enable signals
> > connected correctly? We faced problems with
> > even/odd 16-bit access when
> > we first brought our C5502 board up because of Byte
> > Enable signals not
> > routed properly.
> >
> > -Jeff
> >
> > > I'm doing DMA Transfer on my c5503 System. I have
> >
> > the config as below.
> >
> > > CCR0 is set as:
> > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > DMA_DMACCR_SRCAMODE_CONST,\
> > > DMA_DMACCR_ENDPROG_OFF,\
> > > DMA_DMACCR_REPEAT_OFF, \
> > > DMA_DMACCR_AUTOINIT_ON,\
> > > DMA_DMACCR_EN_STOP,\
> > > DMA_DMACCR_PRIO_HI,\
> > > DMA_DMACCR_FS_ENABLE,\
> > > DMA_DMACCR_SYNC_NONE\
> > > )
> > >
> > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > DMA_DMACSDP_DSTPACK_ON,\
> > > DMA_DMACSDP_DST_DARAM,\
> > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > DMA_DMACSDP_SRCPACK_ON,\
> > > DMA_DMACSDP_SRC_EMIF,\
> > > DMA_DMACSDP_DATATYPE_16BIT )
> > >
> > > Dma runs for word adresses e.g. PTR = 0x0800fd and
> >
> > the source register
> >
> > > is set
> > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > >
> > >
> > > My problem: If I use PTR 0x0800fe the chip enable
> >
> > (ce0 in my case) is
> >
> > > coming
> > > only every 2nd read (the [async] read itself comes
> >
> > as it should). Result:
> > > Onyl half the values are read!
> > >
> > > If I use cpu acess, the PTR adress can be read in
> >
> > any case properly.
> >
> > > Is it so, that even word adresses won't work? The
> >
> > Dma-spreadsheet says:
> > > "The DMA controller makes 16-bit accesses at the
> >
> > source and at the
> >
> > > destination. The source and destination start
> >
> > addresses must each be
> >
> > > on an even 2-byte boundary; the least significant
> >
> > bit (LSB) must be 0:"
> >
> > > So do they refer to the word or byte adress? In my
> >
> > config odd word
> >
> > > adresses
> > > work properly, while even won't do so.
> > >
> > > Thanks in advance for your comments
> > >
> > > Michael
> > > P.S:
> > > (the config alltogether is:)
> > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > DMA_RSET(DMACEN0, 8);
> > > DMA_RSET(DMACFN0, 1);
> > > DMA_RSET(DMACDSAL0, (((Uint32)
> >
> > DMA_1_PTR)<<1)&0xFFFF);
> >
> > > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)&
> >
> > 0xFFFF);
> >
> > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > > DMA_RSET(DMACICR0,CICR_VAL);
> > > // 2*N+1 = 3 Words
> > > DMA_RSET(DMACSEI0, 7);
> > > // programm end
> > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > // start dma
> > > DMA_FSET(DMACCR0, EN, 1);
>
0x0800fe is word adress and its the source adress.
Also it's shifted left, so there should be no difference between 0x800fe and
0x800fd refering to odd or even (or do I misunderstand something?)
Michael
Am Montag, 16. Januar 2006 15:36 schrieb Lakshman:
> Hi Michael,
>
> This feature of C55x is known as packing/unpacking on
> the fly; DMA can pack or unpack the data...If you pass
> odd address (0x0800fe) as destination address, the
> values at destination address are unpacked...means a
> 16-bit memory will have a byte data.
>
> Best Regards,
> -Lakshman
>
> --- Jeff Brower <jbrower@jbro...> wrote:
> > Michael-
> >
> > Is this with external SRAM? If so, do you have Byte
> > Enable signals
> > connected correctly? We faced problems with
> > even/odd 16-bit access when
> > we first brought our C5502 board up because of Byte
> > Enable signals not
> > routed properly.
> >
> > -Jeff
> >
> > > I'm doing DMA Transfer on my c5503 System. I have
> >
> > the config as below.
> >
> > > CCR0 is set as:
> > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > DMA_DMACCR_SRCAMODE_CONST,\
> > > DMA_DMACCR_ENDPROG_OFF,\
> > > DMA_DMACCR_REPEAT_OFF, \
> > > DMA_DMACCR_AUTOINIT_ON,\
> > > DMA_DMACCR_EN_STOP,\
> > > DMA_DMACCR_PRIO_HI,\
> > > DMA_DMACCR_FS_ENABLE,\
> > > DMA_DMACCR_SYNC_NONE\
> > > )
> > >
> > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > DMA_DMACSDP_DSTPACK_ON,\
> > > DMA_DMACSDP_DST_DARAM,\
> > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > DMA_DMACSDP_SRCPACK_ON,\
> > > DMA_DMACSDP_SRC_EMIF,\
> > > DMA_DMACSDP_DATATYPE_16BIT )
> > >
> > > Dma runs for word adresses e.g. PTR = 0x0800fd and
> >
> > the source register
> >
> > > is set
> > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > >
> > >
> > > My problem: If I use PTR 0x0800fe the chip enable
> >
> > (ce0 in my case) is
> >
> > > coming
> > > only every 2nd read (the [async] read itself comes
> >
> > as it should). Result:
> > > Onyl half the values are read!
> > >
> > > If I use cpu acess, the PTR adress can be read in
> >
> > any case properly.
> >
> > > Is it so, that even word adresses won't work? The
> >
> > Dma-spreadsheet says:
> > > "The DMA controller makes 16-bit accesses at the
> >
> > source and at the
> >
> > > destination. The source and destination start
> >
> > addresses must each be
> >
> > > on an even 2-byte boundary; the least significant
> >
> > bit (LSB) must be 0:"
> >
> > > So do they refer to the word or byte adress? In my
> >
> > config odd word
> >
> > > adresses
> > > work properly, while even won't do so.
> > >
> > > Thanks in advance for your comments
> > >
> > > Michael
> > > P.S:
> > > (the config alltogether is:)
> > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > DMA_RSET(DMACEN0, 8);
> > > DMA_RSET(DMACFN0, 1);
> > > DMA_RSET(DMACDSAL0, (((Uint32)
> >
> > DMA_1_PTR)<<1)&0xFFFF);
> >
> > > DMA_RSET(DMACDSAU0, (((Uint32) DMA_1_PTR)>>15)&
> >
> > 0xFFFF);
> >
> > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) & 0xFFFF);
> > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)& 0xFFFF);
> > > DMA_RSET(DMACICR0,CICR_VAL);
> > > // 2*N+1 = 3 Words
> > > DMA_RSET(DMACSEI0, 7);
> > > // programm end
> > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > // start dma
> > > DMA_FSET(DMACCR0, EN, 1);
>
Reply by ●January 18, 20062006-01-18
Hi Michael,
they might be changing the src/dst adress within CSL
calls. Just single step into CSL calls and check where
the address is incremented by 1. That solves the
problem...
BR,
-Lakshman --- Michael Schuster <schuster@schu...> wrote:
> Hi Lakshma,
> 0x0800fe is word adress and its the source adress.
> Also it's shifted left, so there should be no
> difference between 0x800fe and
> 0x800fd refering to odd or even (or do I
> misunderstand something?)
>
> Michael
> Am Montag, 16. Januar 2006 15:36 schrieb Lakshman:
> > Hi Michael,
> >
> > This feature of C55x is known as packing/unpacking
> on
> > the fly; DMA can pack or unpack the data...If you
> pass
> > odd address (0x0800fe) as destination address, the
> > values at destination address are unpacked...means
> a
> > 16-bit memory will have a byte data.
> >
> > Best Regards,
> > -Lakshman
> >
> > --- Jeff Brower <jbrower@jbro...> wrote:
> > > Michael-
> > >
> > > Is this with external SRAM? If so, do you have
> Byte
> > > Enable signals
> > > connected correctly? We faced problems with
> > > even/odd 16-bit access when
> > > we first brought our C5502 board up because of
> Byte
> > > Enable signals not
> > > routed properly.
> > >
> > > -Jeff
> > >
> > > > I'm doing DMA Transfer on my c5503 System. I
> have
> > >
> > > the config as below.
> > >
> > > > CCR0 is set as:
> > > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > > DMA_DMACCR_SRCAMODE_CONST,\
> > > > DMA_DMACCR_ENDPROG_OFF,\
> > > > DMA_DMACCR_REPEAT_OFF, \
> > > > DMA_DMACCR_AUTOINIT_ON,\
> > > > DMA_DMACCR_EN_STOP,\
> > > > DMA_DMACCR_PRIO_HI,\
> > > > DMA_DMACCR_FS_ENABLE,\
> > > > DMA_DMACCR_SYNC_NONE\
> > > > )
> > > >
> > > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > > DMA_DMACSDP_DSTPACK_ON,\
> > > > DMA_DMACSDP_DST_DARAM,\
> > > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > > DMA_DMACSDP_SRCPACK_ON,\
> > > > DMA_DMACSDP_SRC_EMIF,\
> > > > DMA_DMACSDP_DATATYPE_16BIT )
> > > >
> > > > Dma runs for word adresses e.g. PTR = 0x0800fd
> and
> > >
> > > the source register
> > >
> > > > is set
> > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) &
> 0xFFFF);
> > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)&
> 0xFFFF);
> > > >
> > > >
> > > > My problem: If I use PTR 0x0800fe the chip
> enable
> > >
> > > (ce0 in my case) is
> > >
> > > > coming
> > > > only every 2nd read (the [async] read itself
> comes
> > >
> > > as it should). Result:
> > > > Onyl half the values are read!
> > > >
> > > > If I use cpu acess, the PTR adress can be read
> in
> > >
> > > any case properly.
> > >
> > > > Is it so, that even word adresses won't work?
> The
> > >
> > > Dma-spreadsheet says:
> > > > "The DMA controller makes 16-bit accesses at
> the
> > >
> > > source and at the
> > >
> > > > destination. The source and destination start
> > >
> > > addresses must each be
> > >
> > > > on an even 2-byte boundary; the least
> significant
> > >
> > > bit (LSB) must be 0:"
> > >
> > > > So do they refer to the word or byte adress?
> In my
> > >
> > > config odd word
> > >
> > > > adresses
> > > > work properly, while even won't do so.
> > > >
> > > > Thanks in advance for your comments
> > > >
> > > > Michael
> > > > P.S:
> > > > (the config alltogether is:)
> > > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > > DMA_RSET(DMACEN0, 8);
> > > > DMA_RSET(DMACFN0, 1);
> > > > DMA_RSET(DMACDSAL0, (((Uint32)
> > >
> > > DMA_1_PTR)<<1)&0xFFFF);
> > >
> > > > DMA_RSET(DMACDSAU0, (((Uint32)
> DMA_1_PTR)>>15)&
> > >
> > > 0xFFFF);
> > >
> > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) &
> 0xFFFF);
> > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)&
> 0xFFFF);
> > > > DMA_RSET(DMACICR0,CICR_VAL);
> > > > // 2*N+1 = 3 Words
> > > > DMA_RSET(DMACSEI0, 7);
> > > > // programm end
> > > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > > // start dma
> > > > DMA_FSET(DMACCR0, EN, 1);
they might be changing the src/dst adress within CSL
calls. Just single step into CSL calls and check where
the address is incremented by 1. That solves the
problem...
BR,
-Lakshman --- Michael Schuster <schuster@schu...> wrote:
> Hi Lakshma,
> 0x0800fe is word adress and its the source adress.
> Also it's shifted left, so there should be no
> difference between 0x800fe and
> 0x800fd refering to odd or even (or do I
> misunderstand something?)
>
> Michael
> Am Montag, 16. Januar 2006 15:36 schrieb Lakshman:
> > Hi Michael,
> >
> > This feature of C55x is known as packing/unpacking
> on
> > the fly; DMA can pack or unpack the data...If you
> pass
> > odd address (0x0800fe) as destination address, the
> > values at destination address are unpacked...means
> a
> > 16-bit memory will have a byte data.
> >
> > Best Regards,
> > -Lakshman
> >
> > --- Jeff Brower <jbrower@jbro...> wrote:
> > > Michael-
> > >
> > > Is this with external SRAM? If so, do you have
> Byte
> > > Enable signals
> > > connected correctly? We faced problems with
> > > even/odd 16-bit access when
> > > we first brought our C5502 board up because of
> Byte
> > > Enable signals not
> > > routed properly.
> > >
> > > -Jeff
> > >
> > > > I'm doing DMA Transfer on my c5503 System. I
> have
> > >
> > > the config as below.
> > >
> > > > CCR0 is set as:
> > > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > > DMA_DMACCR_SRCAMODE_CONST,\
> > > > DMA_DMACCR_ENDPROG_OFF,\
> > > > DMA_DMACCR_REPEAT_OFF, \
> > > > DMA_DMACCR_AUTOINIT_ON,\
> > > > DMA_DMACCR_EN_STOP,\
> > > > DMA_DMACCR_PRIO_HI,\
> > > > DMA_DMACCR_FS_ENABLE,\
> > > > DMA_DMACCR_SYNC_NONE\
> > > > )
> > > >
> > > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > > DMA_DMACSDP_DSTPACK_ON,\
> > > > DMA_DMACSDP_DST_DARAM,\
> > > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > > DMA_DMACSDP_SRCPACK_ON,\
> > > > DMA_DMACSDP_SRC_EMIF,\
> > > > DMA_DMACSDP_DATATYPE_16BIT )
> > > >
> > > > Dma runs for word adresses e.g. PTR = 0x0800fd
> and
> > >
> > > the source register
> > >
> > > > is set
> > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) &
> 0xFFFF);
> > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)&
> 0xFFFF);
> > > >
> > > >
> > > > My problem: If I use PTR 0x0800fe the chip
> enable
> > >
> > > (ce0 in my case) is
> > >
> > > > coming
> > > > only every 2nd read (the [async] read itself
> comes
> > >
> > > as it should). Result:
> > > > Onyl half the values are read!
> > > >
> > > > If I use cpu acess, the PTR adress can be read
> in
> > >
> > > any case properly.
> > >
> > > > Is it so, that even word adresses won't work?
> The
> > >
> > > Dma-spreadsheet says:
> > > > "The DMA controller makes 16-bit accesses at
> the
> > >
> > > source and at the
> > >
> > > > destination. The source and destination start
> > >
> > > addresses must each be
> > >
> > > > on an even 2-byte boundary; the least
> significant
> > >
> > > bit (LSB) must be 0:"
> > >
> > > > So do they refer to the word or byte adress?
> In my
> > >
> > > config odd word
> > >
> > > > adresses
> > > > work properly, while even won't do so.
> > > >
> > > > Thanks in advance for your comments
> > > >
> > > > Michael
> > > > P.S:
> > > > (the config alltogether is:)
> > > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > > DMA_RSET(DMACEN0, 8);
> > > > DMA_RSET(DMACFN0, 1);
> > > > DMA_RSET(DMACDSAL0, (((Uint32)
> > >
> > > DMA_1_PTR)<<1)&0xFFFF);
> > >
> > > > DMA_RSET(DMACDSAU0, (((Uint32)
> DMA_1_PTR)>>15)&
> > >
> > > 0xFFFF);
> > >
> > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) &
> 0xFFFF);
> > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)&
> 0xFFFF);
> > > > DMA_RSET(DMACICR0,CICR_VAL);
> > > > // 2*N+1 = 3 Words
> > > > DMA_RSET(DMACSEI0, 7);
> > > > // programm end
> > > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > > // start dma
> > > > DMA_FSET(DMACCR0, EN, 1);
Reply by ●January 19, 20062006-01-19
Hi Lakshman,
I didnot use CSL calls - just plain Register programming as posted.
Also, I tested it with an other board, to eliminate a hardware defect. The src
is configured to be const, soI can't explain the toggling of Adress A1 while
reading from this const src adress, which I have seen on my oszi during the
dma transfer...
Michael Am Mittwoch, 18. Januar 2006 10:06 schrieb Lakshman:
> Hi Michael,
>
> they might be changing the src/dst adress within CSL
> calls. Just single step into CSL calls and check where
> the address is incremented by 1. That solves the
> problem...
>
> BR,
> -Lakshman
>
> --- Michael Schuster <schuster@schu...> wrote:
> > Hi Lakshma,
> > 0x0800fe is word adress and its the source adress.
> > Also it's shifted left, so there should be no
> > difference between 0x800fe and
> > 0x800fd refering to odd or even (or do I
> > misunderstand something?)
> >
> > Michael
> >
> > Am Montag, 16. Januar 2006 15:36 schrieb Lakshman:
> > > Hi Michael,
> > >
> > > This feature of C55x is known as packing/unpacking
> >
> > on
> >
> > > the fly; DMA can pack or unpack the data...If you
> >
> > pass
> >
> > > odd address (0x0800fe) as destination address, the
> > > values at destination address are unpacked...means
> >
> > a
> >
> > > 16-bit memory will have a byte data.
> > >
> > > Best Regards,
> > > -Lakshman
> > >
> > > --- Jeff Brower <jbrower@jbro...> wrote:
> > > > Michael-
> > > >
> > > > Is this with external SRAM? If so, do you have
> >
> > Byte
> >
> > > > Enable signals
> > > > connected correctly? We faced problems with
> > > > even/odd 16-bit access when
> > > > we first brought our C5502 board up because of
> >
> > Byte
> >
> > > > Enable signals not
> > > > routed properly.
> > > >
> > > > -Jeff
> > > >
> > > > > I'm doing DMA Transfer on my c5503 System. I
> >
> > have
> >
> > > > the config as below.
> > > >
> > > > > CCR0 is set as:
> > > > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > > > DMA_DMACCR_SRCAMODE_CONST,\
> > > > > DMA_DMACCR_ENDPROG_OFF,\
> > > > > DMA_DMACCR_REPEAT_OFF, \
> > > > > DMA_DMACCR_AUTOINIT_ON,\
> > > > > DMA_DMACCR_EN_STOP,\
> > > > > DMA_DMACCR_PRIO_HI,\
> > > > > DMA_DMACCR_FS_ENABLE,\
> > > > > DMA_DMACCR_SYNC_NONE\
> > > > > )
> > > > >
> > > > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > > > DMA_DMACSDP_DSTPACK_ON,\
> > > > > DMA_DMACSDP_DST_DARAM,\
> > > > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > > > DMA_DMACSDP_SRCPACK_ON,\
> > > > > DMA_DMACSDP_SRC_EMIF,\
> > > > > DMA_DMACSDP_DATATYPE_16BIT )
> > > > >
> > > > > Dma runs for word adresses e.g. PTR = 0x0800fd
> >
> > and
> >
> > > > the source register
> > > >
> > > > > is set
> > > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) &
> >
> > 0xFFFF);
> >
> > > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)&
> >
> > 0xFFFF);
> >
> > > > > My problem: If I use PTR 0x0800fe the chip
> >
> > enable
> >
> > > > (ce0 in my case) is
> > > >
> > > > > coming
> > > > > only every 2nd read (the [async] read itself
> >
> > comes
> >
> > > > as it should). Result:
> > > > > Onyl half the values are read!
> > > > >
> > > > > If I use cpu acess, the PTR adress can be read
> >
> > in
> >
> > > > any case properly.
> > > >
> > > > > Is it so, that even word adresses won't work?
> >
> > The
> >
> > > > Dma-spreadsheet says:
> > > > > "The DMA controller makes 16-bit accesses at
> >
> > the
> >
> > > > source and at the
> > > >
> > > > > destination. The source and destination start
> > > >
> > > > addresses must each be
> > > >
> > > > > on an even 2-byte boundary; the least
> >
> > significant
> >
> > > > bit (LSB) must be 0:"
> > > >
> > > > > So do they refer to the word or byte adress?
> >
> > In my
> >
> > > > config odd word
> > > >
> > > > > adresses
> > > > > work properly, while even won't do so.
> > > > >
> > > > > Thanks in advance for your comments
> > > > >
> > > > > Michael
> > > > > P.S:
> > > > > (the config alltogether is:)
> > > > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > > > DMA_RSET(DMACEN0, 8);
> > > > > DMA_RSET(DMACFN0, 1);
> > > > > DMA_RSET(DMACDSAL0, (((Uint32)
> > > >
> > > > DMA_1_PTR)<<1)&0xFFFF);
> > > >
> > > > > DMA_RSET(DMACDSAU0, (((Uint32)
> >
> > DMA_1_PTR)>>15)&
> >
> > > > 0xFFFF);
> > > >
> > > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) &
> >
> > 0xFFFF);
> >
> > > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)&
> >
> > 0xFFFF);
> >
> > > > > DMA_RSET(DMACICR0,CICR_VAL);
> > > > > // 2*N+1 = 3 Words
> > > > > DMA_RSET(DMACSEI0, 7);
> > > > > // programm end
> > > > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > > > // start dma
> > > > > DMA_FSET(DMACCR0, EN, 1);
I didnot use CSL calls - just plain Register programming as posted.
Also, I tested it with an other board, to eliminate a hardware defect. The src
is configured to be const, soI can't explain the toggling of Adress A1 while
reading from this const src adress, which I have seen on my oszi during the
dma transfer...
Michael Am Mittwoch, 18. Januar 2006 10:06 schrieb Lakshman:
> Hi Michael,
>
> they might be changing the src/dst adress within CSL
> calls. Just single step into CSL calls and check where
> the address is incremented by 1. That solves the
> problem...
>
> BR,
> -Lakshman
>
> --- Michael Schuster <schuster@schu...> wrote:
> > Hi Lakshma,
> > 0x0800fe is word adress and its the source adress.
> > Also it's shifted left, so there should be no
> > difference between 0x800fe and
> > 0x800fd refering to odd or even (or do I
> > misunderstand something?)
> >
> > Michael
> >
> > Am Montag, 16. Januar 2006 15:36 schrieb Lakshman:
> > > Hi Michael,
> > >
> > > This feature of C55x is known as packing/unpacking
> >
> > on
> >
> > > the fly; DMA can pack or unpack the data...If you
> >
> > pass
> >
> > > odd address (0x0800fe) as destination address, the
> > > values at destination address are unpacked...means
> >
> > a
> >
> > > 16-bit memory will have a byte data.
> > >
> > > Best Regards,
> > > -Lakshman
> > >
> > > --- Jeff Brower <jbrower@jbro...> wrote:
> > > > Michael-
> > > >
> > > > Is this with external SRAM? If so, do you have
> >
> > Byte
> >
> > > > Enable signals
> > > > connected correctly? We faced problems with
> > > > even/odd 16-bit access when
> > > > we first brought our C5502 board up because of
> >
> > Byte
> >
> > > > Enable signals not
> > > > routed properly.
> > > >
> > > > -Jeff
> > > >
> > > > > I'm doing DMA Transfer on my c5503 System. I
> >
> > have
> >
> > > > the config as below.
> > > >
> > > > > CCR0 is set as:
> > > > > #define CCR0_VAL DMA_DMACCR_RMK(\
> > > > > DMA_DMACCR_DSTAMODE_SGLINDX,\
> > > > > DMA_DMACCR_SRCAMODE_CONST,\
> > > > > DMA_DMACCR_ENDPROG_OFF,\
> > > > > DMA_DMACCR_REPEAT_OFF, \
> > > > > DMA_DMACCR_AUTOINIT_ON,\
> > > > > DMA_DMACCR_EN_STOP,\
> > > > > DMA_DMACCR_PRIO_HI,\
> > > > > DMA_DMACCR_FS_ENABLE,\
> > > > > DMA_DMACCR_SYNC_NONE\
> > > > > )
> > > > >
> > > > > #define CSDP0_VAL DMA_DMACSDP_RMK( \
> > > > > DMA_DMACSDP_DSTBEN_BURST4,\
> > > > > DMA_DMACSDP_DSTPACK_ON,\
> > > > > DMA_DMACSDP_DST_DARAM,\
> > > > > DMA_DMACSDP_SRCBEN_BURST4,\
> > > > > DMA_DMACSDP_SRCPACK_ON,\
> > > > > DMA_DMACSDP_SRC_EMIF,\
> > > > > DMA_DMACSDP_DATATYPE_16BIT )
> > > > >
> > > > > Dma runs for word adresses e.g. PTR = 0x0800fd
> >
> > and
> >
> > > > the source register
> > > >
> > > > > is set
> > > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) &
> >
> > 0xFFFF);
> >
> > > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)&
> >
> > 0xFFFF);
> >
> > > > > My problem: If I use PTR 0x0800fe the chip
> >
> > enable
> >
> > > > (ce0 in my case) is
> > > >
> > > > > coming
> > > > > only every 2nd read (the [async] read itself
> >
> > comes
> >
> > > > as it should). Result:
> > > > > Onyl half the values are read!
> > > > >
> > > > > If I use cpu acess, the PTR adress can be read
> >
> > in
> >
> > > > any case properly.
> > > >
> > > > > Is it so, that even word adresses won't work?
> >
> > The
> >
> > > > Dma-spreadsheet says:
> > > > > "The DMA controller makes 16-bit accesses at
> >
> > the
> >
> > > > source and at the
> > > >
> > > > > destination. The source and destination start
> > > >
> > > > addresses must each be
> > > >
> > > > > on an even 2-byte boundary; the least
> >
> > significant
> >
> > > > bit (LSB) must be 0:"
> > > >
> > > > > So do they refer to the word or byte adress?
> >
> > In my
> >
> > > > config odd word
> > > >
> > > > > adresses
> > > > > work properly, while even won't do so.
> > > > >
> > > > > Thanks in advance for your comments
> > > > >
> > > > > Michael
> > > > > P.S:
> > > > > (the config alltogether is:)
> > > > > DMA_RSET(DMACCR0, CCR0_VAL);
> > > > > DMA_RSET(DMACSDP0, CSDP0_VAL);
> > > > > DMA_RSET(DMACEN0, 8);
> > > > > DMA_RSET(DMACFN0, 1);
> > > > > DMA_RSET(DMACDSAL0, (((Uint32)
> > > >
> > > > DMA_1_PTR)<<1)&0xFFFF);
> > > >
> > > > > DMA_RSET(DMACDSAU0, (((Uint32)
> >
> > DMA_1_PTR)>>15)&
> >
> > > > 0xFFFF);
> > > >
> > > > > DMA_RSET(DMACSSAL0, (((Uint32) PTR)<<1) &
> >
> > 0xFFFF);
> >
> > > > > DMA_RSET(DMACSSAU0, (((Uint32) PTR)>>15)&
> >
> > 0xFFFF);
> >
> > > > > DMA_RSET(DMACICR0,CICR_VAL);
> > > > > // 2*N+1 = 3 Words
> > > > > DMA_RSET(DMACSEI0, 7);
> > > > > // programm end
> > > > > DMA_FSET(DMACCR0, ENDPROG, 1);
> > > > > // start dma
> > > > > DMA_FSET(DMACCR0, EN, 1);
