I have two very similar boards that I need to work with in my debugger
with Spectrum Digital 510USB jtag device and CCS 3.1.
The primary difference is that the V1 board uses a Samsung
K6X8016T3B-TF55 chip providing 1MB of SRAM, and the V2 board uses a
Samsung K4S561632E-TI75 chip providing 32MB of SDRAM.
When I was given the V1 board, someone else set up my CCS environment
for me. Now I've been given the V2 board, and I'm trying to adjust
for
the new environment.
When I try to load a program into memory, It pushes a large portion of
the program into memory, and then I gt an error dialog saying "Data
verification failed at address 0x80079F60. Please verify target memory
and memory map." Can someone point me to instructions on how to
interpret the correct settings for each of my memory chips?
The old working gel file had this information in the init_emif() function.
#define EMIF_GCTL 0x01800000
#define EMIF_CE1 0x01800004
#define EMIF_CE0 0x01800008
#define EMIF_CE2 0x01800010
#define EMIF_CE3 0x01800014
#define EMIF_SDRAMCTL 0x01800018
#define EMIF_SDRAMTIM 0x0180001C
#define EMIF_SDRAMEXT 0x01800020
#define EMIF_CCFG 0x01840000; // Cache configuration register
/* EMIF setup */
*(int *)EMIF_GCTL = 0x00003F78;
*(int *)EMIF_CE0 = 0x11514511; // CE0 SDRAM
*(int *)EMIF_CE1 = 0x21624502; // CE1 Flash 8-bit
*(int *)EMIF_CE2 = 0x10914202; // CE2 Daughtercard 32-bit async
*(int *)EMIF_CE3 = 0x10934423; // CE3 Daughtercard 32-bit async
if (Get_Board_Rev == 2)
{
*(int *)EMIF_SDRAMCTL = 0x57115000; // SDRAM control (16 Mb)
}
else
{
*(int *)EMIF_SDRAMCTL = 0x47115000; // SDRAM control (8 Mb)
}
*(int *)EMIF_SDRAMTIM = 0x00000578; // SDRAM timing (refresh)
*(int *)EMIF_SDRAMEXT = 0x000a8529; // SDRAM Extension register
The new information that's not working as I was given:
*(int *)EMIF_GCTL = 0x00003078; /* EMIF global ctrl */
*(int *)EMIF_CE0 = 0x00000090; /* CE0 = SDRAM 16 */
*(int *)EMIF_CE1 = 0x21624502; /* CE1 = async 8 */
*(int *)EMIF_CE2 = 0x10914202; /* CE2 = async 8 */
*(int *)EMIF_CE3 = 0x10414110; /* CE3 = async 16 */
*(int *)EMIF_SDRAMTIM = 0x005DC5DC; /* SDRAM Refresh Timing
*/
*(int *)EMIF_SDRAMEXT = 0x0004B428; /* SDRAM extended Control */
*(int *)EMIF_SDRAMCTL = 0x63116000; /* SDRAM Control */
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video
Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
Where to find instructions on EMIF configuration in GEL file
Started by ●February 6, 2008
Reply by ●February 6, 20082008-02-06
Hello Wim,
On 2/6/08, William C Bonner wrote:
>
> I have two very similar boards that I need to work with in my debugger
> with Spectrum Digital 510USB jtag device and CCS 3.1.
>
> The primary difference is that the V1 board uses a Samsung
> K6X8016T3B-TF55 chip providing 1MB of SRAM, and the V2 board uses a
> Samsung K4S561632E-TI75 chip providing 32MB of SDRAM.
>
> When I was given the V1 board, someone else set up my CCS environment
> for me. Now I've been given the V2 board, and I'm trying to adjust for
> the new environment.
>
> When I try to load a program into memory, It pushes a large portion of
> the program into memory, and then I gt an error dialog saying "Data
> verification failed at address 0x80079F60. Please verify target memory
> and memory map." Can someone point me to instructions on how to
> interpret the correct settings for each of my memory chips?
>
Go to ti.com and and find 'spru190'. This doc will point you to the EMIF doc
for your DSP [you didn't mention which DSP]. You can set the timing
parameters for SDRAM [they *may* have an example for your SDRAM]. You will
need data sheets for both devices if you have to do it 'the hard way'
[decode the data sheet into EMIF settings]. You can use the original
setup/data sheet to verify your understanding [FYI- I have found some
'working' settings to be incorrect and they were working 'by luck' causing
occaisional random failures]. Also take care if you copy settings - if they
were for a different EMIF clock rate they might need to be tweaked.
SDRAMCTL, SDRAMTIM, SDRAMEXT, and EMIF_CE0 are the suspects to look at.
mikedunn
The old working gel file had this information in the init_emif()
> function.
>
> #define EMIF_GCTL 0x01800000
> #define EMIF_CE1 0x01800004
> #define EMIF_CE0 0x01800008
> #define EMIF_CE2 0x01800010
> #define EMIF_CE3 0x01800014
> #define EMIF_SDRAMCTL 0x01800018
> #define EMIF_SDRAMTIM 0x0180001C
> #define EMIF_SDRAMEXT 0x01800020
> #define EMIF_CCFG 0x01840000; // Cache configuration register
>
> /* EMIF setup */
> *(int *)EMIF_GCTL = 0x00003F78;
> *(int *)EMIF_CE0 = 0x11514511; // CE0 SDRAM
> *(int *)EMIF_CE1 = 0x21624502; // CE1 Flash 8-bit
> *(int *)EMIF_CE2 = 0x10914202; // CE2 Daughtercard 32-bit async
> *(int *)EMIF_CE3 = 0x10934423; // CE3 Daughtercard 32-bit async
> if (Get_Board_Rev == 2)
> {
> *(int *)EMIF_SDRAMCTL = 0x57115000; // SDRAM control (16 Mb)
> }
> else
> {
> *(int *)EMIF_SDRAMCTL = 0x47115000; // SDRAM control (8 Mb)
> }
> *(int *)EMIF_SDRAMTIM = 0x00000578; // SDRAM timing (refresh)
> *(int *)EMIF_SDRAMEXT = 0x000a8529; // SDRAM Extension register
>
> The new information that's not working as I was given:
> *(int *)EMIF_GCTL = 0x00003078; /* EMIF global ctrl */
> *(int *)EMIF_CE0 = 0x00000090; /* CE0 = SDRAM 16 */
> *(int *)EMIF_CE1 = 0x21624502; /* CE1 = async 8 */
> *(int *)EMIF_CE2 = 0x10914202; /* CE2 = async 8 */
> *(int *)EMIF_CE3 = 0x10414110; /* CE3 = async 16 */
> *(int *)EMIF_SDRAMTIM = 0x005DC5DC; /* SDRAM Refresh Timing
> */
> *(int *)EMIF_SDRAMEXT = 0x0004B428; /* SDRAM extended Control */
> *(int *)EMIF_SDRAMCTL = 0x63116000; /* SDRAM Control */
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On 2/6/08, William C Bonner wrote:
>
> I have two very similar boards that I need to work with in my debugger
> with Spectrum Digital 510USB jtag device and CCS 3.1.
>
> The primary difference is that the V1 board uses a Samsung
> K6X8016T3B-TF55 chip providing 1MB of SRAM, and the V2 board uses a
> Samsung K4S561632E-TI75 chip providing 32MB of SDRAM.
>
> When I was given the V1 board, someone else set up my CCS environment
> for me. Now I've been given the V2 board, and I'm trying to adjust for
> the new environment.
>
> When I try to load a program into memory, It pushes a large portion of
> the program into memory, and then I gt an error dialog saying "Data
> verification failed at address 0x80079F60. Please verify target memory
> and memory map." Can someone point me to instructions on how to
> interpret the correct settings for each of my memory chips?
>
Go to ti.com and and find 'spru190'. This doc will point you to the EMIF doc
for your DSP [you didn't mention which DSP]. You can set the timing
parameters for SDRAM [they *may* have an example for your SDRAM]. You will
need data sheets for both devices if you have to do it 'the hard way'
[decode the data sheet into EMIF settings]. You can use the original
setup/data sheet to verify your understanding [FYI- I have found some
'working' settings to be incorrect and they were working 'by luck' causing
occaisional random failures]. Also take care if you copy settings - if they
were for a different EMIF clock rate they might need to be tweaked.
SDRAMCTL, SDRAMTIM, SDRAMEXT, and EMIF_CE0 are the suspects to look at.
mikedunn
The old working gel file had this information in the init_emif()
> function.
>
> #define EMIF_GCTL 0x01800000
> #define EMIF_CE1 0x01800004
> #define EMIF_CE0 0x01800008
> #define EMIF_CE2 0x01800010
> #define EMIF_CE3 0x01800014
> #define EMIF_SDRAMCTL 0x01800018
> #define EMIF_SDRAMTIM 0x0180001C
> #define EMIF_SDRAMEXT 0x01800020
> #define EMIF_CCFG 0x01840000; // Cache configuration register
>
> /* EMIF setup */
> *(int *)EMIF_GCTL = 0x00003F78;
> *(int *)EMIF_CE0 = 0x11514511; // CE0 SDRAM
> *(int *)EMIF_CE1 = 0x21624502; // CE1 Flash 8-bit
> *(int *)EMIF_CE2 = 0x10914202; // CE2 Daughtercard 32-bit async
> *(int *)EMIF_CE3 = 0x10934423; // CE3 Daughtercard 32-bit async
> if (Get_Board_Rev == 2)
> {
> *(int *)EMIF_SDRAMCTL = 0x57115000; // SDRAM control (16 Mb)
> }
> else
> {
> *(int *)EMIF_SDRAMCTL = 0x47115000; // SDRAM control (8 Mb)
> }
> *(int *)EMIF_SDRAMTIM = 0x00000578; // SDRAM timing (refresh)
> *(int *)EMIF_SDRAMEXT = 0x000a8529; // SDRAM Extension register
>
> The new information that's not working as I was given:
> *(int *)EMIF_GCTL = 0x00003078; /* EMIF global ctrl */
> *(int *)EMIF_CE0 = 0x00000090; /* CE0 = SDRAM 16 */
> *(int *)EMIF_CE1 = 0x21624502; /* CE1 = async 8 */
> *(int *)EMIF_CE2 = 0x10914202; /* CE2 = async 8 */
> *(int *)EMIF_CE3 = 0x10414110; /* CE3 = async 16 */
> *(int *)EMIF_SDRAMTIM = 0x005DC5DC; /* SDRAM Refresh Timing
> */
> *(int *)EMIF_SDRAMEXT = 0x0004B428; /* SDRAM extended Control */
> *(int *)EMIF_SDRAMCTL = 0x63116000; /* SDRAM Control */
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●February 6, 20082008-02-06
William,
the SDRAM parameters look reasonable. SDRAM requires a clock, which is
typically connected to the DSP ECLKOUT pin.
Please verify this clock is configured correctly (I assume you are using a
6713 board):
- if ECLKOUT is derived from the on-chip PLL:
DEVCFG register, bit 4 must be cleared,
PLL divider DIV3 must be programmed to generate the required clock
(typically 100 MHz)
- if ECLKOUT is driven by an external oscillator connected to ECLKIN:
DEVCFG, bit 4 must be set
Also, a DSP reset in CCS will reset the EMIF configuration. You may call
the EMIF initialization in the GEL OnReset() function.
Best Regards,
Adolf Klemenz, D.SignT
At 05:13 06.02.2008 -0800, William C Bonner wrote:
>I have two very similar boards that I need to work with in my debugger
>with Spectrum Digital 510USB jtag device and CCS 3.1.
>
>The primary difference is that the V1 board uses a Samsung
>K6X8016T3B-TF55 chip providing 1MB of SRAM, and the V2 board uses a
>Samsung K4S561632E-TI75 chip providing 32MB of SDRAM.
>
>When I was given the V1 board, someone else set up my CCS environment
>for me. Now I've been given the V2 board, and I'm trying to adjust for
>the new environment.
>
>When I try to load a program into memory, It pushes a large portion of
>the program into memory, and then I gt an error dialog saying "Data
>verification failed at address 0x80079F60. Please verify target memory
>and memory map." Can someone point me to instructions on how to
>interpret the correct settings for each of my memory chips?
>
>The old working gel file had this information in the init_emif() function.
>
>#define EMIF_GCTL 0x01800000
>#define EMIF_CE1 0x01800004
>#define EMIF_CE0 0x01800008
>#define EMIF_CE2 0x01800010
>#define EMIF_CE3 0x01800014
>#define EMIF_SDRAMCTL 0x01800018
>#define EMIF_SDRAMTIM 0x0180001C
>#define EMIF_SDRAMEXT 0x01800020
>#define EMIF_CCFG 0x01840000; // Cache configuration register
>
>/* EMIF setup */
>*(int *)EMIF_GCTL = 0x00003F78;
>*(int *)EMIF_CE0 = 0x11514511; // CE0 SDRAM
>*(int *)EMIF_CE1 = 0x21624502; // CE1 Flash 8-bit
>*(int *)EMIF_CE2 = 0x10914202; // CE2 Daughtercard 32-bit async
>*(int *)EMIF_CE3 = 0x10934423; // CE3 Daughtercard 32-bit async
>if (Get_Board_Rev == 2)
>{
>*(int *)EMIF_SDRAMCTL = 0x57115000; // SDRAM control (16 Mb)
>}
>else
>{
>*(int *)EMIF_SDRAMCTL = 0x47115000; // SDRAM control (8 Mb)
>}
>*(int *)EMIF_SDRAMTIM = 0x00000578; // SDRAM timing (refresh)
>*(int *)EMIF_SDRAMEXT = 0x000a8529; // SDRAM Extension register
>
>The new information that's not working as I was given:
>*(int *)EMIF_GCTL = 0x00003078; /* EMIF global ctrl */
>*(int *)EMIF_CE0 = 0x00000090; /* CE0 = SDRAM 16 */
>*(int *)EMIF_CE1 = 0x21624502; /* CE1 = async 8 */
>*(int *)EMIF_CE2 = 0x10914202; /* CE2 = async 8 */
>*(int *)EMIF_CE3 = 0x10414110; /* CE3 = async 16 */
>*(int *)EMIF_SDRAMTIM = 0x005DC5DC; /* SDRAM Refresh Timing
>*/
>*(int *)EMIF_SDRAMEXT = 0x0004B428; /* SDRAM extended Control */
>*(int *)EMIF_SDRAMCTL = 0x63116000; /* SDRAM Control */
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
the SDRAM parameters look reasonable. SDRAM requires a clock, which is
typically connected to the DSP ECLKOUT pin.
Please verify this clock is configured correctly (I assume you are using a
6713 board):
- if ECLKOUT is derived from the on-chip PLL:
DEVCFG register, bit 4 must be cleared,
PLL divider DIV3 must be programmed to generate the required clock
(typically 100 MHz)
- if ECLKOUT is driven by an external oscillator connected to ECLKIN:
DEVCFG, bit 4 must be set
Also, a DSP reset in CCS will reset the EMIF configuration. You may call
the EMIF initialization in the GEL OnReset() function.
Best Regards,
Adolf Klemenz, D.SignT
At 05:13 06.02.2008 -0800, William C Bonner wrote:
>I have two very similar boards that I need to work with in my debugger
>with Spectrum Digital 510USB jtag device and CCS 3.1.
>
>The primary difference is that the V1 board uses a Samsung
>K6X8016T3B-TF55 chip providing 1MB of SRAM, and the V2 board uses a
>Samsung K4S561632E-TI75 chip providing 32MB of SDRAM.
>
>When I was given the V1 board, someone else set up my CCS environment
>for me. Now I've been given the V2 board, and I'm trying to adjust for
>the new environment.
>
>When I try to load a program into memory, It pushes a large portion of
>the program into memory, and then I gt an error dialog saying "Data
>verification failed at address 0x80079F60. Please verify target memory
>and memory map." Can someone point me to instructions on how to
>interpret the correct settings for each of my memory chips?
>
>The old working gel file had this information in the init_emif() function.
>
>#define EMIF_GCTL 0x01800000
>#define EMIF_CE1 0x01800004
>#define EMIF_CE0 0x01800008
>#define EMIF_CE2 0x01800010
>#define EMIF_CE3 0x01800014
>#define EMIF_SDRAMCTL 0x01800018
>#define EMIF_SDRAMTIM 0x0180001C
>#define EMIF_SDRAMEXT 0x01800020
>#define EMIF_CCFG 0x01840000; // Cache configuration register
>
>/* EMIF setup */
>*(int *)EMIF_GCTL = 0x00003F78;
>*(int *)EMIF_CE0 = 0x11514511; // CE0 SDRAM
>*(int *)EMIF_CE1 = 0x21624502; // CE1 Flash 8-bit
>*(int *)EMIF_CE2 = 0x10914202; // CE2 Daughtercard 32-bit async
>*(int *)EMIF_CE3 = 0x10934423; // CE3 Daughtercard 32-bit async
>if (Get_Board_Rev == 2)
>{
>*(int *)EMIF_SDRAMCTL = 0x57115000; // SDRAM control (16 Mb)
>}
>else
>{
>*(int *)EMIF_SDRAMCTL = 0x47115000; // SDRAM control (8 Mb)
>}
>*(int *)EMIF_SDRAMTIM = 0x00000578; // SDRAM timing (refresh)
>*(int *)EMIF_SDRAMEXT = 0x000a8529; // SDRAM Extension register
>
>The new information that's not working as I was given:
>*(int *)EMIF_GCTL = 0x00003078; /* EMIF global ctrl */
>*(int *)EMIF_CE0 = 0x00000090; /* CE0 = SDRAM 16 */
>*(int *)EMIF_CE1 = 0x21624502; /* CE1 = async 8 */
>*(int *)EMIF_CE2 = 0x10914202; /* CE2 = async 8 */
>*(int *)EMIF_CE3 = 0x10414110; /* CE3 = async 16 */
>*(int *)EMIF_SDRAMTIM = 0x005DC5DC; /* SDRAM Refresh Timing
>*/
>*(int *)EMIF_SDRAMEXT = 0x0004B428; /* SDRAM extended Control */
>*(int *)EMIF_SDRAMCTL = 0x63116000; /* SDRAM Control */
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
Reply by ●February 9, 20082008-02-09
Thanks for the information. Yes this is all related to a 6713 based
system (TMS320C6713) and I normally try to include that information in
my posts so that when I'm web searching for things a year from now I'll
be more likely to find relevant information.
See my other response to the list for the information about what my
underlying problem really was. I may be initializing the EMIF slightly
wrong, but the bigger problem has to do with the hardware watchdog
rebooting my board in the middle of my uploading software over the JTAG.
I wrote some code using the functions that requested the
config from a running program, and then prints the output to the serial
port in hex. I'm on a plane right now, and I forget to get the latest
version of code transferred to my laptop so I can't include the exact
code. Assuming that the EMIF gets set correctly by the original process
that starts my board during power up, should I be able to retrieve all
of the correct settings for my gell file in this fashion? I wasn't sure
if some of the bits may be in a different state at runtime than they
should be initialized to when starting the board?
I still have intermittent problems debugging the board using CCS and the
JTAG connection. Sometimes when I've been running fine in the debugger
and have halted the system at a break point, realizing what the problem
is I fix the code, rebuild and push the code into the device, and then
start running, but for some reason the board doesn't respond to
interrupts. (Sorry for the run on sentence.) Halting the processor
followed by recompiling and pushing the code generally makes it work.
I've got CCS configured to push the code over the JTAG automatically
after a successful build, as it makes my dev process seem much faster in
general.
If you think these symptoms may be related to incorrect parameters, or
even function calls or sequences in my GEL file, I'll post that question
with the results of querying any of the registers in my running system
that may give useful information.
Thanks for all the input. Wim.
Adolf Klemenz wrote:
> William,
>
> the SDRAM parameters look reasonable. SDRAM requires a clock, which is
> typically connected to the DSP ECLKOUT pin.
>
> Please verify this clock is configured correctly (I assume you are using a
> 6713 board):
>
> - if ECLKOUT is derived from the on-chip PLL:
> DEVCFG register, bit 4 must be cleared,
> PLL divider DIV3 must be programmed to generate the required clock
> (typically 100 MHz)
> - if ECLKOUT is driven by an external oscillator connected to ECLKIN:
> DEVCFG, bit 4 must be set
>
> Also, a DSP reset in CCS will reset the EMIF configuration. You may call
> the EMIF initialization in the GEL OnReset() function.
>
> Best Regards,
> Adolf Klemenz, D.SignT
> At 05:13 06.02.2008 -0800, William C Bonner wrote:
>
>
>> I have two very similar boards that I need to work with in my debugger
>> with Spectrum Digital 510USB jtag device and CCS 3.1.
>>
>> The primary difference is that the V1 board uses a Samsung
>> K6X8016T3B-TF55 chip providing 1MB of SRAM, and the V2 board uses a
>> Samsung K4S561632E-TI75 chip providing 32MB of SDRAM.
>>
>> When I was given the V1 board, someone else set up my CCS environment
>> for me. Now I've been given the V2 board, and I'm trying to adjust for
>> the new environment.
>>
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
system (TMS320C6713) and I normally try to include that information in
my posts so that when I'm web searching for things a year from now I'll
be more likely to find relevant information.
See my other response to the list for the information about what my
underlying problem really was. I may be initializing the EMIF slightly
wrong, but the bigger problem has to do with the hardware watchdog
rebooting my board in the middle of my uploading software over the JTAG.
I wrote some code using the functions that requested the
config from a running program, and then prints the output to the serial
port in hex. I'm on a plane right now, and I forget to get the latest
version of code transferred to my laptop so I can't include the exact
code. Assuming that the EMIF gets set correctly by the original process
that starts my board during power up, should I be able to retrieve all
of the correct settings for my gell file in this fashion? I wasn't sure
if some of the bits may be in a different state at runtime than they
should be initialized to when starting the board?
I still have intermittent problems debugging the board using CCS and the
JTAG connection. Sometimes when I've been running fine in the debugger
and have halted the system at a break point, realizing what the problem
is I fix the code, rebuild and push the code into the device, and then
start running, but for some reason the board doesn't respond to
interrupts. (Sorry for the run on sentence.) Halting the processor
followed by recompiling and pushing the code generally makes it work.
I've got CCS configured to push the code over the JTAG automatically
after a successful build, as it makes my dev process seem much faster in
general.
If you think these symptoms may be related to incorrect parameters, or
even function calls or sequences in my GEL file, I'll post that question
with the results of querying any of the registers in my running system
that may give useful information.
Thanks for all the input. Wim.
Adolf Klemenz wrote:
> William,
>
> the SDRAM parameters look reasonable. SDRAM requires a clock, which is
> typically connected to the DSP ECLKOUT pin.
>
> Please verify this clock is configured correctly (I assume you are using a
> 6713 board):
>
> - if ECLKOUT is derived from the on-chip PLL:
> DEVCFG register, bit 4 must be cleared,
> PLL divider DIV3 must be programmed to generate the required clock
> (typically 100 MHz)
> - if ECLKOUT is driven by an external oscillator connected to ECLKIN:
> DEVCFG, bit 4 must be set
>
> Also, a DSP reset in CCS will reset the EMIF configuration. You may call
> the EMIF initialization in the GEL OnReset() function.
>
> Best Regards,
> Adolf Klemenz, D.SignT
> At 05:13 06.02.2008 -0800, William C Bonner wrote:
>
>
>> I have two very similar boards that I need to work with in my debugger
>> with Spectrum Digital 510USB jtag device and CCS 3.1.
>>
>> The primary difference is that the V1 board uses a Samsung
>> K6X8016T3B-TF55 chip providing 1MB of SRAM, and the V2 board uses a
>> Samsung K4S561632E-TI75 chip providing 32MB of SDRAM.
>>
>> When I was given the V1 board, someone else set up my CCS environment
>> for me. Now I've been given the V2 board, and I'm trying to adjust for
>> the new environment.
>>
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
Reply by ●February 9, 20082008-02-09
Michael Dunn wrote:
> Hello Wim,
>
> On 2/6/08, William C Bonner wrote:
>
>> I have two very similar boards that I need to work with in my debugger
>> with Spectrum Digital 510USB jtag device and CCS 3.1.
>>
>> The primary difference is that the V1 board uses a Samsung
>> K6X8016T3B-TF55 chip providing 1MB of SRAM, and the V2 board uses a
>> Samsung K4S561632E-TI75 chip providing 32MB of SDRAM.
>>
> Go to ti.com and and find 'spru190'. This doc will point you to the EMIF doc
> for your DSP [you didn't mention which DSP]. You can set the timing
> parameters for SDRAM [they *may* have an example for your SDRAM]. You will
> need data sheets for both devices if you have to do it 'the hard way'
> [decode the data sheet into EMIF settings]. You can use the original
> setup/data sheet to verify your understanding [FYI- I have found some
> 'working' settings to be incorrect and they were working 'by luck' causing
> occaisional random failures]. Also take care if you copy settings - if they
> were for a different EMIF clock rate they might need to be tweaked.
> SDRAMCTL, SDRAMTIM, SDRAMEXT, and EMIF_CE0 are the suspects to look at.
>
> mikedunn
>
>
Thanks for pointing me at that document. It got me to the right place
to understand the EMIF registers. In the latest versions of the
documents, the chapters that were in the old document are mostly split
out into separate documents. After spending the better part of two days
decoding bitmaps and reading data sheets I understand my hardware much
better than I did early in the week.
The funny thing is that the problem I was having was not based on the
problem I had with the EMIF commands in my GEL file, but instead was
based on the fact that I was not disabling the hardware watchdog on the
board that I was trying to debug. The V1 boards that I was using had a
mistake in the manufacturing and the watchdog was not correctly
configured to be able to reset the board. Consequently it didn't matter
if I had jumpered the watchdog disable pins or not while I was
debugging. The V2 boards fix this problem, so it's the first time I'm
really having to make sure that I plug the watchdog often enough, but
more importantly I need to disable it during debugging.
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
> Hello Wim,
>
> On 2/6/08, William C Bonner wrote:
>
>> I have two very similar boards that I need to work with in my debugger
>> with Spectrum Digital 510USB jtag device and CCS 3.1.
>>
>> The primary difference is that the V1 board uses a Samsung
>> K6X8016T3B-TF55 chip providing 1MB of SRAM, and the V2 board uses a
>> Samsung K4S561632E-TI75 chip providing 32MB of SDRAM.
>>
> Go to ti.com and and find 'spru190'. This doc will point you to the EMIF doc
> for your DSP [you didn't mention which DSP]. You can set the timing
> parameters for SDRAM [they *may* have an example for your SDRAM]. You will
> need data sheets for both devices if you have to do it 'the hard way'
> [decode the data sheet into EMIF settings]. You can use the original
> setup/data sheet to verify your understanding [FYI- I have found some
> 'working' settings to be incorrect and they were working 'by luck' causing
> occaisional random failures]. Also take care if you copy settings - if they
> were for a different EMIF clock rate they might need to be tweaked.
> SDRAMCTL, SDRAMTIM, SDRAMEXT, and EMIF_CE0 are the suspects to look at.
>
> mikedunn
>
>
Thanks for pointing me at that document. It got me to the right place
to understand the EMIF registers. In the latest versions of the
documents, the chapters that were in the old document are mostly split
out into separate documents. After spending the better part of two days
decoding bitmaps and reading data sheets I understand my hardware much
better than I did early in the week.
The funny thing is that the problem I was having was not based on the
problem I had with the EMIF commands in my GEL file, but instead was
based on the fact that I was not disabling the hardware watchdog on the
board that I was trying to debug. The V1 boards that I was using had a
mistake in the manufacturing and the watchdog was not correctly
configured to be able to reset the board. Consequently it didn't matter
if I had jumpered the watchdog disable pins or not while I was
debugging. The V2 boards fix this problem, so it's the first time I'm
really having to make sure that I plug the watchdog often enough, but
more importantly I need to disable it during debugging.
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
