Hi all!
I am a hardware newbie. We have designed a system using two tms320c6455
and altera arriax fpga, the system is working well. I mean that we can
use jtag to debug the dsp and fpga. But there are some problems, I list
them in the following:
1.we directly connect 6455's emif port to fpga. what do we have to do
before 6455 can successfully communicate with fpga? Is there any
reference design or examples?
2.there are some RAMs in fpga, could we config it as a dual-port memory
(one port for fpga, the other for dsp)?
because I have no idea about how to it, maybe my description is not
very clear, but thank you very much for any suggestions!
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video
Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
some questions about dsp and fpga system, need sugestion
Started by ●March 1, 2008
Reply by ●March 2, 20082008-03-02
dsp6455,
On Fri, Feb 29, 2008 at 8:08 PM, dsp6455 wrote:
> Hi all!
> I am a hardware newbie. We have designed a system using two tms320c6455
> and altera arriax fpga, the system is working well. I mean that we can
> use jtag to debug the dsp and fpga. But there are some problems, I list
> them in the following:
> 1.we directly connect 6455's emif port to fpga. what do we have to do
> before 6455 can successfully communicate with fpga?
Although I am unclear about your architecture and goals, I will
provide some comments.
Hopefully you have put the FPGA on a separate CE space from any
synchronous memory. If you have done so, just initialize that CE
space for async memory and add any wait states needed. If you are
using a GEL file during debug, you can do it there. You should then be
able to r/w the FPGA from CCS or a DSP program.
> Is there any
> reference design or examples?
It seems to be a little later to be looking for a reference design.
You can probably find an example in the 6455 DSK schematics. The
hookup is the same for any r/w peripheral.
> 2.there are some RAMs in fpga, could we config it as a dual-port memory
> (one port for fpga, the other for dsp)?
No problem as long as the pins are wired right. The DSP can r/w - the
FPGA can be programmed to to anything that will fit.
>
> because I have no idea about how to it, maybe my description is not
> very clear, but thank you very much for any suggestions!
Don't get caught up in technical stuff when trying to describe what
you want to do. Keep in mind that we have no idea of your architecture
- you need to say enough to paint a picture of your architecture in
our mind. Something like [I don't know if this applies exactly to
you]:
I need to run 'whiz-bang' algorithms at n Mhz whcich is faster than my
DSP. I have an FPGA connected to the EMIF of my 6455 DSP. I want to
put some memory between the DSP's EMIF and the 'whiz-bang-magic-logic'
in my FPGA that is accessed by both the DSP and the EMIF. Is this
possible.
mikedunn
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
On Fri, Feb 29, 2008 at 8:08 PM, dsp6455 wrote:
> Hi all!
> I am a hardware newbie. We have designed a system using two tms320c6455
> and altera arriax fpga, the system is working well. I mean that we can
> use jtag to debug the dsp and fpga. But there are some problems, I list
> them in the following:
> 1.we directly connect 6455's emif port to fpga. what do we have to do
> before 6455 can successfully communicate with fpga?
Although I am unclear about your architecture and goals, I will
provide some comments.
Hopefully you have put the FPGA on a separate CE space from any
synchronous memory. If you have done so, just initialize that CE
space for async memory and add any wait states needed. If you are
using a GEL file during debug, you can do it there. You should then be
able to r/w the FPGA from CCS or a DSP program.
> Is there any
> reference design or examples?
It seems to be a little later to be looking for a reference design.
You can probably find an example in the 6455 DSK schematics. The
hookup is the same for any r/w peripheral.
> 2.there are some RAMs in fpga, could we config it as a dual-port memory
> (one port for fpga, the other for dsp)?
No problem as long as the pins are wired right. The DSP can r/w - the
FPGA can be programmed to to anything that will fit.
>
> because I have no idea about how to it, maybe my description is not
> very clear, but thank you very much for any suggestions!
Don't get caught up in technical stuff when trying to describe what
you want to do. Keep in mind that we have no idea of your architecture
- you need to say enough to paint a picture of your architecture in
our mind. Something like [I don't know if this applies exactly to
you]:
I need to run 'whiz-bang' algorithms at n Mhz whcich is faster than my
DSP. I have an FPGA connected to the EMIF of my 6455 DSP. I want to
put some memory between the DSP's EMIF and the 'whiz-bang-magic-logic'
in my FPGA that is accessed by both the DSP and the EMIF. Is this
possible.
mikedunn
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
