Looking at new floating point DSP. (tms320c6747)

FYI -

I don't know if you guys have noticed - TI has finally posted the
c6747 datasheet [I'm not sure when, I checked today after seeing an
announcement somewhere].

It is definitely based on the c64+
"Superset of the C67x+ and C64x+ ISAs"

mikedunn

On Wed, Sep 10, 2008 at 1:18 PM, Jeff Brower wrote:
> Mike-
>
>> My 2 cents,
>>
>> The features below tell me that it is a c64+ with floating point.
>> Instruction Packing Reduces Code Size
>> Hardware Support for Modulo Loop
>> Protected Mode Operation
>> Comprehensive System-Wide Security Operation
>
> Instruction packing is a tip-off, for sure. But it's still not clear to me, because
> otherwise there should be an obvious 2x increase in performance. Maybe the
> situation is that fixed-point operations use the Joule core technology, but
> floating-point doesn't?
>
> -Jeff
>
>> On Wed, Sep 10, 2008 at 10:57 AM, Jeff Brower wrote:
>> > Mike-
>> >
>> >>
>> >> The computation speeds look identical for the same clock speed. The
>> >> real benefits will show up in other places.
>> >
>> > Hmm... did you guys decide that the C6747 does have 64x+ type core? Or does not; i.e. is similar to C6713?
>> >
>> > -Jeff
>> >
>> >>> Thanks for correcting where I was looking. I had been looking at the tables
>> >>> on this page http://focus.ti.com/docs/prod/folders/print/tms320c6713b.html
>> >>> and this page http://focus.ti.com/docs/prod/folders/print/tms320c6745.html
>> >>> and comparing what I could find that matched. That was Peak MMACS. What are
>> >>> MMACS used for in comparison purposes?
>> >>
>> >> MMACs - Millions of Multiply ACumulates per Second
>> >> I have only seen these in DSPs. Since many algos use multiply - add
>> >> loops and early DSPs required separate cycles for each, companies
>> >> could show performance advantages if there was no additional time
>> >> required for the adds [accumulates].
>> >>
>> >> The bottom line is still how well your code performs. If you have
>> >> some time critical loops [don't we all :-) ], you can probably get a
>> >> simulator for the c674x for CCS 3.3 [Historically TI has had one
>> >> available at announcement]. If you are a registered CCS 3.3 user, you
>> >> can go to the CCS update site and see if it is listed [it would be
>> >> something like 'c674x CSP'].
>> >>
>> >> My personal opion on simulators [in all fairness I am not much of a
>> >> simulator user]:
>> >> 1. Don't run apps on simulators, just algorithms.
>> >> 2. Rely on them for 'loop cycles', not total system performance.
>> >> 3. External memory timings don't seem to correlate so good.
>> >> 4. Run apples-to-apples tests. Run test code on the 6713 sim and the
>> >> 674x sim. If the algo is 15% faster on the sim it will execute 15%
>> >> faster on the hardware [with the same memory environment].
>> >>
>> >> mikedunn
>> >>> (FLOPS I completely understand, and
>> >>> MIPS don't make sense with scaled architectures. I'm working with lots of
>> >>> floating point operations, so am currently dependent on the floating point
>> >>> procesors)
>> >>>
>> >>> Wim.
>> >>>
>> >>> On Tue, Sep 9, 2008 at 4:00 PM, Michael Dunn
>> >>> wrote:
>> >>>>
>> >>>> Wim,
>> >>>>
>> >>>> On Tue, Sep 9, 2008 at 5:21 PM, William C Bonner
>> >>>> wrote:
>> >>>> > Well, if MMACS (Million Multiply Accumulate Cycles per Second) are an
>> >>>> > indication, this new chip running at the 200 MHz frequency gets 1600 of
>> >>>> > them, and the 200MHz 6713 that I've been using only gets 400 of them, so
>> >>>> > that's a 4x increase at the same external clock speed.
>> >>>>
>> >>>>
>> >>>> Not exactly.
>> >>>> Your 200Mhz 6713 gets 1600 MIPS/1200 MFLOPS [advertised - see datasheet].
>> >>>>
>> >>>> 2 fix.pt. ALUs, 4 fix/flt pt. ALUs, 2 multipliers all in parallel [if
>> >>>> you can keep them fed :-)
>> >>>>
>> >>>> mikedunn
>> >>>> >
>> >>>> > I was limited to running at the 200MHz speed on my old platform based on
>> >>>> > my
>> >>>> > need for the extended environmental range of -40 to 105, and the new
>> >>>> > chip
>> >>>> > claims to support -40 to 125 at both of it's speeds, so that's another
>> >>>> > benefit to me, allowing me to run at 300MHz and get 2400 MMACS, making
>> >>>> > it a
>> >>>> > 6x speed boost.
>> >
>> >
>>
>> --
>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>
>>
>>
>>
>>
>>
>>
>>

--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php Start a New Thread

Thanks for the information. It may prove useful if they change the status
from PREVIEW to ACTIVE and start showing inventory.
http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?family=dsp§ionId=2&tabId=2232&familyId=1622still
shows them as preview, while
http://focus.ti.com/docs/prod/folders/print/tms320c6745.html shows them as
ACTIVE. Even then, I'm sure that it will take longer to develop a new board
than it's worth for me in the short term, since it would be primarily for
power savings.

Wim.

On Mon, Oct 6, 2008 at 3:46 PM, Michael Dunn wrote:

> FYI -
>
> I don't know if you guys have noticed - TI has finally posted the
> c6747 datasheet [I'm not sure when, I checked today after seeing an
> announcement somewhere].
>
> It is definitely based on the c64+
> "Superset of the C67x+ and C64x+ ISAs"
>
> mikedunn
>
> On Wed, Sep 10, 2008 at 1:18 PM, Jeff Brower
> wrote:
> > Mike-
> >
> >> My 2 cents,
> >>
> >> The features below tell me that it is a c64+ with floating point.
> >> Instruction Packing Reduces Code Size
> >> Hardware Support for Modulo Loop
> >> Protected Mode Operation
> >> Comprehensive System-Wide Security Operation
> >
> > Instruction packing is a tip-off, for sure. But it's still not clear to
> me, because
> > otherwise there should be an obvious 2x increase in performance. Maybe
> the
> > situation is that fixed-point operations use the Joule core technology,
> but
> > floating-point doesn't?
> >
> > -Jeff
> >
> >> On Wed, Sep 10, 2008 at 10:57 AM, Jeff Brower
> wrote:
> >> > Mike-
> >> >
> >> >>
> >> >> The computation speeds look identical for the same clock speed. The
> >> >> real benefits will show up in other places.
> >> >
> >> > Hmm... did you guys decide that the C6747 does have 64x+ type core?
> Or does not; i.e. is similar to C6713?
> >> >
> >> > -Jeff
> >> >
> >> >>> Thanks for correcting where I was looking. I had been looking at
> the tables
> >> >>> on this page
> http://focus.ti.com/docs/prod/folders/print/tms320c6713b.html
> >> >>> and this page
> http://focus.ti.com/docs/prod/folders/print/tms320c6745.html
> >> >>> and comparing what I could find that matched. That was Peak MMACS.
> What are
> >> >>> MMACS used for in comparison purposes?
> >> >>
> >> >> MMACs - Millions of Multiply ACumulates per Second
> >> >> I have only seen these in DSPs. Since many algos use multiply - add
> >> >> loops and early DSPs required separate cycles for each, companies
> >> >> could show performance advantages if there was no additional time
> >> >> required for the adds [accumulates].
> >> >>
> >> >> The bottom line is still how well your code performs. If you have
> >> >> some time critical loops [don't we all :-) ], you can probably get a
> >> >> simulator for the c674x for CCS 3.3 [Historically TI has had one
> >> >> available at announcement]. If you are a registered CCS 3.3 user, you
> >> >> can go to the CCS update site and see if it is listed [it would be
> >> >> something like 'c674x CSP'].
> >> >>
> >> >> My personal opion on simulators [in all fairness I am not much of a
> >> >> simulator user]:
> >> >> 1. Don't run apps on simulators, just algorithms.
> >> >> 2. Rely on them for 'loop cycles', not total system performance.
> >> >> 3. External memory timings don't seem to correlate so good.
> >> >> 4. Run apples-to-apples tests. Run test code on the 6713 sim and the
> >> >> 674x sim. If the algo is 15% faster on the sim it will execute 15%
> >> >> faster on the hardware [with the same memory environment].
> >> >>
> >> >> mikedunn
> >> >>> (FLOPS I completely understand, and
> >> >>> MIPS don't make sense with scaled architectures. I'm working with
> lots of
> >> >>> floating point operations, so am currently dependent on the floating
> point
> >> >>> procesors)
> >> >>>
> >> >>> Wim.
> >> >>>
> >> >>> On Tue, Sep 9, 2008 at 4:00 PM, Michael Dunn <
> m...@gmail.com>
> >> >>> wrote:
> >> >>>>
> >> >>>> Wim,
> >> >>>>
> >> >>>> On Tue, Sep 9, 2008 at 5:21 PM, William C Bonner <
> w...@wimsworld.com>
> >> >>>> wrote:
> >> >>>> > Well, if MMACS (Million Multiply Accumulate Cycles per Second)
> are an
> >> >>>> > indication, this new chip running at the 200 MHz frequency gets
> 1600 of
> >> >>>> > them, and the 200MHz 6713 that I've been using only gets 400 of
> them, so
> >> >>>> > that's a 4x increase at the same external clock speed.
> >> >>>>
> >> >>>>
> >> >>>> Not exactly.
> >> >>>> Your 200Mhz 6713 gets 1600 MIPS/1200 MFLOPS [advertised - see
> datasheet].
> >> >>>>
> >> >>>> 2 fix.pt. ALUs, 4 fix/flt pt. ALUs, 2 multipliers all in parallel
> [if
> >> >>>> you can keep them fed :-)
> >> >>>>
> >> >>>> mikedunn
> >> >>>> >
> >> >>>> > I was limited to running at the 200MHz speed on my old platform
> based on
> >> >>>> > my
> >> >>>> > need for the extended environmental range of -40 to 105, and the
> new
> >> >>>> > chip
> >> >>>> > claims to support -40 to 125 at both of it's speeds, so that's
> another
> >> >>>> > benefit to me, allowing me to run at 300MHz and get 2400 MMACS,
> making
> >> >>>> > it a
> >> >>>> > 6x speed boost.
> >> >
> >> >
> >> Start a New Thread

Wim,

I am not sure if I said it before, but I would not suggest making a
'company bet' on a device without established availability. I have
been involved in a couple of projects that used new devices and
aggressive schedules - enough things go wrong when you think that you
are dealing with 'known constants' [hardware and software].

>From what I have read, the c674x should be a real power miser for the
right apps.

mikedunn

On Mon, Oct 6, 2008 at 7:02 PM, William C Bonner wrote:
> Thanks for the information. It may prove useful if they change the status
> from PREVIEW to ACTIVE and start showing inventory.
> http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?family=dsp§ionId=2&tabId=2232&familyId=1622
> still shows them as preview, while
> http://focus.ti.com/docs/prod/folders/print/tms320c6745.html shows them as
> ACTIVE. Even then, I'm sure that it will take longer to develop a new board
> than it's worth for me in the short term, since it would be primarily for
> power savings.
>
> Wim.
>
> On Mon, Oct 6, 2008 at 3:46 PM, Michael Dunn
> wrote:
>>
>> FYI -
>>
>> I don't know if you guys have noticed - TI has finally posted the
>> c6747 datasheet [I'm not sure when, I checked today after seeing an
>> announcement somewhere].
>>
>> It is definitely based on the c64+
>> "Superset of the C67x+ and C64x+ ISAs"
>>
>> mikedunn
>>
>> On Wed, Sep 10, 2008 at 1:18 PM, Jeff Brower
>> wrote:
>> > Mike-
>> >
>> >> My 2 cents,
>> >>
>> >> The features below tell me that it is a c64+ with floating point.
>> >> Instruction Packing Reduces Code Size
>> >> Hardware Support for Modulo Loop
>> >> Protected Mode Operation
>> >> Comprehensive System-Wide Security Operation
>> >
>> > Instruction packing is a tip-off, for sure. But it's still not clear to
>> > me, because
>> > otherwise there should be an obvious 2x increase in performance. Maybe
>> > the
>> > situation is that fixed-point operations use the Joule core technology,
>> > but
>> > floating-point doesn't?
>> >
>> > -Jeff
>> >
>> >> On Wed, Sep 10, 2008 at 10:57 AM, Jeff Brower
>> >> wrote:
>> >> > Mike-
>> >> >
>> >> >>
>> >> >> The computation speeds look identical for the same clock speed. The
>> >> >> real benefits will show up in other places.
>> >> >
>> >> > Hmm... did you guys decide that the C6747 does have 64x+ type core?
>> >> > Or does not; i.e. is similar to C6713?
>> >> >
>> >> > -Jeff
>> >> >
>> >> >>> Thanks for correcting where I was looking. I had been looking at
>> >> >>> the tables
>> >> >>> on this page
>> >> >>> http://focus.ti.com/docs/prod/folders/print/tms320c6713b.html
>> >> >>> and this page
>> >> >>> http://focus.ti.com/docs/prod/folders/print/tms320c6745.html
>> >> >>> and comparing what I could find that matched. That was Peak MMACS.
>> >> >>> What are
>> >> >>> MMACS used for in comparison purposes?
>> >> >>
>> >> >> MMACs - Millions of Multiply ACumulates per Second
>> >> >> I have only seen these in DSPs. Since many algos use multiply - add
>> >> >> loops and early DSPs required separate cycles for each, companies
>> >> >> could show performance advantages if there was no additional time
>> >> >> required for the adds [accumulates].
>> >> >>
>> >> >> The bottom line is still how well your code performs. If you have
>> >> >> some time critical loops [don't we all :-) ], you can probably get
>> >> >> a
>> >> >> simulator for the c674x for CCS 3.3 [Historically TI has had one
>> >> >> available at announcement]. If you are a registered CCS 3.3 user,
>> >> >> you
>> >> >> can go to the CCS update site and see if it is listed [it would be
>> >> >> something like 'c674x CSP'].
>> >> >>
>> >> >> My personal opion on simulators [in all fairness I am not much of a
>> >> >> simulator user]:
>> >> >> 1. Don't run apps on simulators, just algorithms.
>> >> >> 2. Rely on them for 'loop cycles', not total system performance.
>> >> >> 3. External memory timings don't seem to correlate so good.
>> >> >> 4. Run apples-to-apples tests. Run test code on the 6713 sim and the
>> >> >> 674x sim. If the algo is 15% faster on the sim it will execute 15%
>> >> >> faster on the hardware [with the same memory environment].
>> >> >>
>> >> >> mikedunn
>> >> >>> (FLOPS I completely understand, and
>> >> >>> MIPS don't make sense with scaled architectures. I'm working with
>> >> >>> lots of
>> >> >>> floating point operations, so am currently dependent on the
>> >> >>> floating point
>> >> >>> procesors)
>> >> >>>
>> >> >>> Wim.
>> >> >>>
>> >> >>> On Tue, Sep 9, 2008 at 4:00 PM, Michael Dunn
>> >> >>>
>> >> >>> wrote:
>> >> >>>>
>> >> >>>> Wim,
>> >> >>>>
>> >> >>>> On Tue, Sep 9, 2008 at 5:21 PM, William C Bonner
>> >> >>>>
>> >> >>>> wrote:
>> >> >>>> > Well, if MMACS (Million Multiply Accumulate Cycles per Second)
>> >> >>>> > are an
>> >> >>>> > indication, this new chip running at the 200 MHz frequency gets
>> >> >>>> > 1600 of
>> >> >>>> > them, and the 200MHz 6713 that I've been using only gets 400 of
>> >> >>>> > them, so
>> >> >>>> > that's a 4x increase at the same external clock speed.
>> >> >>>>
>> >> >>>>
>> >> >>>> Not exactly.
>> >> >>>> Your 200Mhz 6713 gets 1600 MIPS/1200 MFLOPS [advertised - see
>> >> >>>> datasheet].
>> >> >>>>
>> >> >>>> 2 fix.pt. ALUs, 4 fix/flt pt. ALUs, 2 multipliers all in parallel
>> >> >>>> [if
>> >> >>>> you can keep them fed :-)
>> >> >>>>
>> >> >>>> mikedunn
>> >> >>>> >
>> >> >>>> > I was limited to running at the 200MHz speed on my old platform
>> >> >>>> > based on
>> >> >>>> > my
>> >> >>>> > need for the extended environmental range of -40 to 105, and the
>> >> >>>> > new
>> >> >>>> > chip
>> >> >>>> > claims to support -40 to 125 at both of it's speeds, so that's
>> >> >>>> > another
>> >> >>>> > benefit to me, allowing me to run at 300MHz and get 2400 MMACS,
>> >> >>>> > making
>> >> >>>> > it a
>> >> >>>> > 6x speed boost.
>> >> >
>> >> > Start a New Thread