C6424 Cache without BIOS

I have an application that is running on a C6424 using the BIOS. I
have the same application running without the BIOS but it runs at
about 1/8 the speed. I'm assuming this has to do with the cache setup.
All the SECTIONS declarations are mapped to the DDR2 memory.

Is there a "simple" way to configure the cache to get this application
running at the speed it does using the BIOS (no BIOS features were
used, just a single task running in a while loop).

Thanks!

Jim Start a New Thread

Jim,

On Mon, Dec 15, 2008 at 2:43 PM, haberly2000 wrote:
>
> I have an application that is running on a C6424 using the BIOS. I
> have the same application running without the BIOS but it runs at
> about 1/8 the speed. I'm assuming this has to do with the cache setup.
> All the SECTIONS declarations are mapped to the DDR2 memory.
>
> Is there a "simple" way to configure the cache to get this application
> running at the speed it does using the BIOS (no BIOS features were
> used, just a single task running in a while loop).


If you are using CSL, you can experiment with cache sizes:
CACHE_L1pSetSize();
CACHE_L1dSetSize();
CACHE_L2SetSize();

You should also look making I/O addresses non-cacheable.
Refer to
TMS320C64x+ DSP Cache User's Guide
for details.

mikedunn
>
> Thanks!
>
> Jim

--
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Jim

On Tue, Dec 16, 2008 at 8:40 AM, haberly2000 wrote:
> Thanks for the reply!
> BTW - When I submitted for help at TI over ISR's without using the
> BIOS they told me that there wasn't a CSL for the C6424 (only a
> register layer CSL)...? Is the cache support routines included in the
> register layer CSL?


If my memory is correct, all that you need to do is 'write a bit
pattern to an address'.
I do not know if the function is defined, but the bit pattern and
address should be.

Refer to
TMS320C64x+ DSP Cache User's Guide
for details.

mikedunn
>
> Here's what I received from TI:
> -
> Thank you for contacting Texas Instruments Technical Support. The
> Service Request #1-615549809 has been assigned to your inquiry.
>
> The DM642 used a functional layer CSL whereas the C6424 uses a
> combination of register layer CSL and PSP (Platform Support Package)
> as its software suite. The functional CSL was created specifically for
> the older DSPs and is configured for the memory map on those parts.
> Because the C6424 contains an entirely different CPU Core, peripheral
> set and memory map the older CSL software will not work.
>
> I do not know of any examples that completely exclude DSP/BIOS from
> the project, but there is a GPIO Interrupt example using the register
> layer CSL and BIOS for C6424 which can be found at the link below.
> -
>
> Jim
> --- In c..., "Michael Dunn" wrote:
>>
>> Jim,
>>
>> On Mon, Dec 15, 2008 at 2:43 PM, haberly2000 wrote:
>> >
>> > I have an application that is running on a C6424 using the BIOS. I
>> > have the same application running without the BIOS but it runs at
>> > about 1/8 the speed. I'm assuming this has to do with the cache setup.
>> > All the SECTIONS declarations are mapped to the DDR2 memory.
>> >
>> > Is there a "simple" way to configure the cache to get this application
>> > running at the speed it does using the BIOS (no BIOS features were
>> > used, just a single task running in a while loop).
>>
>>
>> If you are using CSL, you can experiment with cache sizes:
>> CACHE_L1pSetSize();
>> CACHE_L1dSetSize();
>> CACHE_L2SetSize();
>>
>> You should also look making I/O addresses non-cacheable.
>> Refer to
>> TMS320C64x+ DSP Cache User's Guide
>> for details.
>>
>> mikedunn
>> >
>> > Thanks!
>> >
>> > Jim
>> >
>> >
>>
>> --
>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
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