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Fw: Re: C6713 DSK _ OUTPUTING VIA EMIF

Started by Wave Waves July 18, 2010
Dear Williams,
Thank U very very much for help,
I guess your right but hat about Rulph Chassing's book (C6713+C6416 & APPLICATIONS) that e disccussed about that before. This bokk has a EMIF project for 32 LED (FFTradix2), and I made a PCB for that exact hardware, but I couldn't complete the program (as u told me before,these projects on chassing's book are incomplete).
Ho can I make those LEDs ON & OFF with that hardware ?!!!!!!!!!!
BTW, I read somewhere that we may be able to ue EMIF a a digital I/O. yes ofcourse, not a GPIO .
 
 
Chassing' code:
 
//EMIF.c Illustrates output through EMIF 80-pin connector J4
#define OUTPUT 0xA0000000    //EMIF output address
int *output = (int *)OUTPUT;
void main()
{
 *output = 0x00000001;    //outputs 0x1 to EMIF bus
}
 
 
my code:
 
// main.c *******************

/* Functional Dependencies */
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include
#include

#include "dsk6713.h"
#include "DSK6713_AIC23.h"  //codec-DSK support file
Uint32 fs=DSK6713_AIC23_FREQ_8KHZ; //set sampling rate
#define DSK6713_AIC23_INPUT_MIC 0x0015
#define DSK6713_AIC23_INPUT_LINE 0x0011
Uint16 inputsource=DSK6713_AIC23_INPUT_MIC;
// EMIF DEFINES: ***† SDEXT available only on C621x/C671x devices.
#define EMIF_GCR   0x01800000 /* EMIF global control      */
#define EMIF_CE0     0x01800008  /* EMIF CE0control          */
#define EMIF_CE1  0x01800004 /* EMIF CE1 control         */
#define EMIF_CE2        0x01800010
#define EMIF_CE3        0x01800014
#define EMIF_SDCTRL  0x01800018  /* EMIF SDRAM control       */
#define EMIF_SDRP    0x0180001c  /* EMIF SDRM refresh period */
#define EMIF_SDRAMEXT   0x01800020
 
 //****************
/* definitions for the DSK */
#define IO_PORT 0x90080000   /* address of I/O port, only top byte has valid data */
//********************
 

/* Global Variables */
unsigned int left_in = 0;
unsigned int right_in = 0;
unsigned int left_out = 0;
unsigned int right_out = 0;
unsigned int lclip = 0;
unsigned int rclip = 0;
unsigned int ad1 = 0;
unsigned int ad2 = 0;
unsigned int analogue_in = 0;
unsigned int analogue_out = 0;
unsigned int ledstatus = 0x07000000;
 
/*
 *  ======== main ======= */
 #define OUTPUT 0xA0000000    //EMIF output address
int *output = (int *)OUTPUT;

void main(void)
{
  /* Initializations */
  emif_init();
  comm_intr();
while (1)
{
 *output = 0x0000000F;    //outputs 0x1 to EMIF bus
}
 
}
 
/*
 *  ======== Interrupt Service Routines ======= */
 
 
/*
 *  ======== End of Main ======= */
 
 
 
 
 
 
 
 
 
/*-*/
//EMIF HEADER
/* define EMIF registers  */
 
#define EMIF_GCR   0x01800000 /* EMIF global control      */
#define EMIF_CE0     0x01800008  /* EMIF CE0control          */
#define EMIF_CE1  0x01800004 /* EMIF CE1 control         */
#define EMIF_CE2        0x01800010
#define EMIF_CE3        0x01800014
#define EMIF_SDCTRL  0x01800018  /* EMIF SDRAM control       */
#define EMIF_SDRP    0x0180001c  /* EMIF SDRM refresh period */
#define EMIF_SDRAMEXT   0x01800020
 
/* define McBSP0 registers */
#define McBSP0_DRR      0x18c0000       /* address of data receive reg.           */
#define McBSP0_DXR      0x18c0004       /* address of data transmit reg.          */
#define McBSP0_SPCR     0x18c0008       /* address of serial port contl. reg.     */
#define McBSP0_RCR      0x18c000C       /* address of receive control reg.        */
#define McBSP0_XCR      0x18c0010       /* address of transmit control reg.       */
#define McBSP0_SRGR     0x18c0014       /* address of sample rate generator       */
#define McBSP0_MCR      0x18c0018       /* address of multichannel reg.           */
#define McBSP0_RCER     0x18c001C       /* address of receive channel enable.     */
#define McBSP0_XCER     0x18c0020       /* address of transmit channel enable.    */
#define McBSP0_PCR      0x18c0024       /* address of pin control reg.            */
/* define McBSP1 registers */
#define McBSP1_DRR      0x1900000       /* address of data receive reg.           */
#define McBSP1_DXR      0x1900004       /* address of data transmit reg.          */
#define McBSP1_SPCR     0x1900008       /* address of serial port contl. reg.     */
#define McBSP1_RCR      0x190000C       /* address of receive control reg.        */
#define McBSP1_XCR      0x1900010       /* address of transmit control reg.       */
#define McBSP1_SRGR     0x1900014       /* address of sample rate generator       */
#define McBSP1_MCR      0x1900018       /* address of multichannel reg.           */
#define McBSP1_RCER     0x190001C       /* address of receive channel enable.     */
#define McBSP1_XCER     0x1900020       /* address of transmit channel enable.    */
#define McBSP1_PCR      0x1900024       /* address of pin control reg.            */
/* define L2 cache registers */
#define L2CFG           0x1840000       /* address of L2 config reg               */
#define MAR0            0x1848200       /* address of mem attribute reg           */
/* define interrupt registers                                                     */
#define IMH             0x19c0000       /* Interrupt Multiplexer High   */
#define IML             0x19c0004       /* Interrupt Multiplexer Low              */

 
/* define timer control registers                                          */
#define TIMER0_PRD          0x1940004
#define TIMER0_CTRL         0x1940000
#define TIMER0_COUNT        0x1940008
#define TIMER1_PRD          0x1980004
#define TIMER1_CTRL         0x1980000
#define TIMER1_COUNT        0x1980008
// EDMA Parameter fields
#define OPT 0
#define SRC 1
#define CNT 2
#define DST 3
#define IDX 4
#define LNK 5
// EDMA Parameter addresses
#define EVENT0_PARAMS 0x01A00000
#define EVENT1_PARAMS EVENT0_PARAMS + 0x18
#define EVENT2_PARAMS EVENT1_PARAMS + 0x18
#define EVENT3_PARAMS EVENT2_PARAMS + 0x18
#define EVENT4_PARAMS EVENT3_PARAMS + 0x18
#define EVENT5_PARAMS EVENT4_PARAMS + 0x18
#define EVENT6_PARAMS EVENT5_PARAMS + 0x18
#define EVENT7_PARAMS EVENT6_PARAMS + 0x18
#define EVENT8_PARAMS EVENT7_PARAMS + 0x18
#define EVENT9_PARAMS EVENT8_PARAMS + 0x18
#define EVENTA_PARAMS EVENT9_PARAMS + 0x18
#define EVENTB_PARAMS EVENTA_PARAMS + 0x18
#define EVENTC_PARAMS EVENTB_PARAMS + 0x18
#define EVENTD_PARAMS EVENTC_PARAMS + 0x18
#define EVENTE_PARAMS EVENTD_PARAMS + 0x18
#define EVENTF_PARAMS EVENTE_PARAMS + 0x18
#define EVENTN_PARAMS EVENTF_PARAMS + 0x18
#define EVENTO_PARAMS EVENTN_PARAMS + 0x18
// EDMA Registers
#define PQSR        0x01A0FFE0
#define CIPR        0x01A0FFE4
#define CIER        0x01A0FFE8
#define CCER        0x01A0FFEC
#define ER          0x01A0FFF0
#define EER         0x01A0FFF4
#define ECR         0x01A0FFF8
#define ESR         0x01A0FFFC
// QDMAs
#define QDMA_OPT 0x02000000
#define QDMA_SRC 0x02000004
#define QDMA_CNT 0x02000008
#define QDMA_DST 0x0200000C
#define QDMA_IDX 0x02000010
 
#define QDMA_S_OPT 0x02000020
#define QDMA_S_SRC 0x02000024
#define QDMA_S_CNT 0x02000028
#define QDMA_S_DST 0x0200002C
#define QDMA_S_IDX 0x02000030

/* definitions for the DSK */
#define IO_PORT 0x90080000   /* address of I/O port, only top byte has valid data */
#define INTERNAL_MEM_SIZE (0x3300)>>2
#define EXTERNAL_MEM_SIZE (0x400000)>>2
#define FLASH_SIZE 0x20000
#define POST_SIZE 0x10000
#define INTERNAL_MEM_START 0xc700
#define EXTERNAL_MEM_START 0x80000000
#define SDRAM 0x80000000
#define FLASH_START 0x90000000
#define INTDSK_CE3 0xB0000000
#define POST_END    0x90010000
#define FLASH_ADR1  0x90005555
#define FLASH_ADR2  0x90002AAA
#define FLASH_KEY1  0xAA
#define FLASH_KEY2  0x55
#define FLASH_KEY3  0xA0
#define LED1 0x06000000
#define LED2 0x05000000
#define LED3 0x03000000
#define SW1  0x01000000
#define SW2  0x02000000
#define SW3  0x04000000
#define ALL_A 0xaaaaaaaa
#define ALL_5 0x55555555
#define CE1_8  0xffffff03  /* reg to set CE1 as 8bit async */
#define CE1_32 0xffffff23  /* reg to set CE1 as 32bit async */

 
 
 
 
 
 
 
 
 
BTW,
 

Dear mikedunn Said before :

The default EMIF initialization provided by the DSK GEL file should work. The key initialization for CE2 space is:
write 0x22a28a22 [CE2 Daughtercard 32-bit async] to addr 0x01800010 [EMIF_CE2]
Use a simple test loop - it can be written in C or assembly code.
write 2 patterns [0xAAAAAAAA & 0x55555555 will work] to 0xA0000000 in an infinite loop.

 
You think this is not enough too ?!!!!!!!!!!!!!!!!!!!!!!!!!
 

 
Best Regard.
Thank U Williams
 
wAVe

--- On Tue, 7/13/10, Richard Williams wrote:
From: Richard Williams
Subject: Re: [c6x] C6713 DSK _ OUTPUTING VIA EMIF
To: "Wave Waves" , c...
Date: Tuesday, July 13, 2010, 2:07 AM
 

Wave,

What I'm trying to say is that the EMIF registers need to be properly setup.
Just writing to some address in the memory mapped range of the EMIF will not
have any effect with out first setting up the EMIF registers.
Even with the EMIF registers properly setup, any data event on the interface
occurs at CPU cycle speeds and needs to have the properly control/status signal
response.
This interface is for memory mapped flash and memory mapped ram, etc. not for
use as a peripheral I/O port.

R. Williams

---------- Original Message -----------
From: Wave Waves
To: Richard Williams , c...
Sent: Sat, 10 Jul 2010 23:08:31 -0700 (PDT)
Subject: Re: [c6x] C6713 DSK _ OUTPUTING VIA EMIF

> Dear Williams,
> I had read the spru266e , spra568a , spra733 , spru401j , spru971c ,
> spru984b month ago. I tryied a lot to make low level (zero voltage) on
> EMIF port, but I couldn't ! please help me as always :d do you mean i
> should drive edma registers defore emif !!!
> >  
> > Yours Sincerely,
> >  wAVe
> >  
>
> --- On Sat, 7/10/10, Richard Williams wrote:
>
> From: Richard Williams
> Subject: [c6x] Re: C6713 DSK _ OUTPUTING VIA EMIF
> To: "Wave Waves" , c...
> Date: Saturday, July 10, 2010, 9:35 PM
>
>  
>
> wave,
>
> the EMIF interface is not a set and hold type of interface.
>
> I would suggest reading SPRU266E.pdf
> "TMS320C6000 DSP External Memory Interface".
>
> ---------- Original Message -----------
> From: Wave Waves
> To: r...@lewiscounty.com, c...
> Sent: Sat, 10 Jul 2010 11:39:48 -0700 (PDT)
> Subject: C6713 DSK _ OUTPUTING VIA EMIF
>
> > Dear Williams,
> > As we discussed about driving EMIF before,
> > I tested lots of solutions and prgrams from making an uotput via EMIF .
> > ***
> >  
> >  
> > //EMIF.c Illustrates output through EMIF 80-pin connector J4
> > #define OUTPUT 0xA0000000    //EMIF output address (CE_2 address)
> > int *output = (int *)OUTPUT;
> > void main()
> > {
> >  *output = 0x00000001;    //outputs 0x1 to EMIF bus
> > }
> >  
> >  
> >  
> > ***
> >  
> > Here are the total solutions :
> >
> > 1.writing an asembely within C code like .sect and define 0xA0000000
> > address in cmd file for this section.  
> > 2.using dsp bios for 6713dsk and driving EMIF registers via EMIF
> > manger in cdb file.  
> > 3.the simpleset solution by initialing the EMIF for 6713 dsk on the
> > main as below : (I also attach you this full project,please take a
> > look): I don't see any error or warning for this code but just can not
> > make any low state (zero voltage) on EMIF 80 pins connector.  
> > seriously, how can we write our value to EMIF port/connector
> > ?!!!!!!!!! none of them works practically !!!!!!!!!     // main.c
> *******************
> >
> > /* Functional Dependencies */
> > #include
> > #include
> > #include
> > #include
> > #include
> > #include
> > #include
> > #include
> > #include
> > #include
> > #include
> > #include
> > #include
> > #include
> >
> > #include "dsk6713.h"
> > #include "DSK6713_AIC23.h"  //codec-DSK support file
> > Uint32 fs=DSK6713_AIC23_FREQ_8KHZ; //set sampling rate
> > #define DSK6713_AIC23_INPUT_MIC 0x0015
> > #define DSK6713_AIC23_INPUT_LINE 0x0011
> > Uint16 inputsource=DSK6713_AIC23_INPUT_MIC;
> > // EMIF DEFINES: [UTF-8?][UTF-8?]***† SDEXT available only on
C621x/C671x devices.
> > #define EMIF_GCR   0x01800000 /* EMIF global control      */
> > #define EMIF_CE0     0x01800008  /* EMIF CE0control          */
> > #define EMIF_CE1  0x01800004 /* EMIF CE1 control         */
> > #define EMIF_CE2        0x01800010
> > #define EMIF_CE3        0x01800014
> > #define EMIF_SDCTRL  0x01800018  /* EMIF SDRAM control       */
> > #define EMIF_SDRP    0x0180001c  /* EMIF SDRM refresh period */
> > #define EMIF_SDRAMEXT   0x01800020
> >  
> >  //****************
> > /* definitions for the DSK */
> > #define IO_PORT 0x90080000   /* address of I/O port, only top byte has valid
> data */
> > //********************
> > /*
> >  *  ======== main =======> >  */
> >  #define OUTPUT 0xA0000000    //EMIF output address
> > int *output = (int *)OUTPUT;
> >
> > void main(void)
> > {
> >   /* Initializations */
> >   emif_init();
> >   comm_intr();
> > while (1)
> > {
> >  *output = 0x0000000F;    //outputs 0x1 to EMIF bus
> > }
> >  
> > }
> >  
> >  
> >  
> >  
> > =================> > ===============> >  
> > Yours Sincerely,
> >  wAVe
> >  
> ------- End of Original Message -------
------- End of Original Message -------