Hello Everyone,
Does anyone know what is the interface used to connect the Virtex-5 FPGA and
the the DSK6416 EMIF ?
I know the connector to be used on the EMIF side is a Samtec TMS
140-32-S-D-LC but I have no idea about interfacing that with the Virtex-5.
The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't
the
same.
Thanks,
--
Varun
Virtex 5 EVM and DSK 6416 EMIF interface
Started by ●July 22, 2010
Reply by ●July 22, 20102010-07-22
Varun-
> Does anyone know what is the interface used to connect the Virtex-5 FPGA and
> the the DSK6416 EMIF ?
>
> I know the connector to be used on the EMIF side is a Samtec TMS
> 140-32-S-D-LC but I have no idea about interfacing that with the Virtex-5.
>
> The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't the
> same.
A couple of initial questions / comments:
1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM? What type of cable are you using?
2) Suggest to post to the group a two-column signal table, one column for EMIF and other for V5 EVM, like this:
DSK6461 EMIF Virtex-5 EVM
------------ ------------
AWE
CEn
ARDY
A2-Am Ai-Aj
D0-Dk D0-Dk
where n, m, and i,j,k are to be determined, the objective being to define signal equivalence and connectivity. There
is no point to worry about number of pins without first carefully considering the underlying design.
-Jeff
_____________________________________
> Does anyone know what is the interface used to connect the Virtex-5 FPGA and
> the the DSK6416 EMIF ?
>
> I know the connector to be used on the EMIF side is a Samtec TMS
> 140-32-S-D-LC but I have no idea about interfacing that with the Virtex-5.
>
> The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't the
> same.
A couple of initial questions / comments:
1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM? What type of cable are you using?
2) Suggest to post to the group a two-column signal table, one column for EMIF and other for V5 EVM, like this:
DSK6461 EMIF Virtex-5 EVM
------------ ------------
AWE
CEn
ARDY
A2-Am Ai-Aj
D0-Dk D0-Dk
where n, m, and i,j,k are to be determined, the objective being to define signal equivalence and connectivity. There
is no point to worry about number of pins without first carefully considering the underlying design.
-Jeff
_____________________________________
Reply by ●August 17, 20102010-08-17
Dear Mr.Bower,
First of all, apologies for the really late reply as I fell sick.
I have posted my replies with *.*
A couple of initial questions / comments:
1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM?
What type of cable are you using?
*: Less than 4 inches. Since we are going to stack the DSP and FIFO one
above the other in order to reduce the cable length.*
2) Suggest to post to the group a two-column signal table, one column for
EMIF and other for V5 EVM, like this:
* Since some glue logic is required I have pasted the image below that
describes the connectivity between the FPGA and the EMIF.*
As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
[image: fifo2emif.bmp]
But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the SDRAM
of the DSK 6416. This means that I need to perform a Peripheral Device
Transfer(PDT). Perform a PDT involves a different kind of interfacing.
[image: PDT.JPG]
*When I looked up the DSK 6416 datasheet, I can't look up for the PDT pin on
the EMIF A. Is the PDT pin an internal pin ??*
*
*
*Thanks,*
*
*
*Varun*
On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower wrote:
> Varun-
>
> > Does anyone know what is the interface used to connect the Virtex-5 FPGA
> and
> > the the DSK6416 EMIF ?
> >
> > I know the connector to be used on the EMIF side is a Samtec TMS
> > 140-32-S-D-LC but I have no idea about interfacing that with the
> Virtex-5.
> >
> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't the
> > same.
>
> A couple of initial questions / comments:
>
> 1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM?
> What type of cable are you using?
>
> 2) Suggest to post to the group a two-column signal table, one column for
> EMIF and other for V5 EVM, like this:
>
> DSK6461 EMIF Virtex-5 EVM
> ------------ ------------
> AWE
> CEn
> ARDY
> A2-Am Ai-Aj
> D0-Dk D0-Dk
>
> where n, m, and i,j,k are to be determined, the objective being to define
> signal equivalence and connectivity. There
> is no point to worry about number of pins without first carefully
> considering the underlying design.
>
> -Jeff
--
Varun
First of all, apologies for the really late reply as I fell sick.
I have posted my replies with *.*
A couple of initial questions / comments:
1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM?
What type of cable are you using?
*: Less than 4 inches. Since we are going to stack the DSP and FIFO one
above the other in order to reduce the cable length.*
2) Suggest to post to the group a two-column signal table, one column for
EMIF and other for V5 EVM, like this:
* Since some glue logic is required I have pasted the image below that
describes the connectivity between the FPGA and the EMIF.*
As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
[image: fifo2emif.bmp]
But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the SDRAM
of the DSK 6416. This means that I need to perform a Peripheral Device
Transfer(PDT). Perform a PDT involves a different kind of interfacing.
[image: PDT.JPG]
*When I looked up the DSK 6416 datasheet, I can't look up for the PDT pin on
the EMIF A. Is the PDT pin an internal pin ??*
*
*
*Thanks,*
*
*
*Varun*
On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower wrote:
> Varun-
>
> > Does anyone know what is the interface used to connect the Virtex-5 FPGA
> and
> > the the DSK6416 EMIF ?
> >
> > I know the connector to be used on the EMIF side is a Samtec TMS
> > 140-32-S-D-LC but I have no idea about interfacing that with the
> Virtex-5.
> >
> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't the
> > same.
>
> A couple of initial questions / comments:
>
> 1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM?
> What type of cable are you using?
>
> 2) Suggest to post to the group a two-column signal table, one column for
> EMIF and other for V5 EVM, like this:
>
> DSK6461 EMIF Virtex-5 EVM
> ------------ ------------
> AWE
> CEn
> ARDY
> A2-Am Ai-Aj
> D0-Dk D0-Dk
>
> where n, m, and i,j,k are to be determined, the objective being to define
> signal equivalence and connectivity. There
> is no point to worry about number of pins without first carefully
> considering the underlying design.
>
> -Jeff
--
Varun
Reply by ●August 18, 20102010-08-18
Varoonian-
> First of all, apologies for the really late reply as I fell sick.
>
> I have posted my replies with *.*
>
> A couple of initial questions / comments:
>
> 1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM?
> What type of cable are you using?
>
> *: Less than 4 inches. Since we are going to stack the DSP and FIFO one
> above the other in order to reduce the cable length.*
>
> 2) Suggest to post to the group a two-column signal table, one column for
> EMIF and other for V5 EVM, like this:
>
> * Since some glue logic is required I have pasted the image below that
> describes the connectivity between the FPGA and the EMIF.*
>
> As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
>
> [image: fifo2emif.bmp]
>
> But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the SDRAM
> of the DSK 6416. This means that I need to perform a Peripheral Device
> Transfer(PDT). Perform a PDT involves a different kind of interfacing.
>
> [image: PDT.JPG]
>
> *When I looked up the DSK 6416 datasheet, I can't look up for the PDT pin on
> the EMIF A. Is the PDT pin an internal pin ??*
/APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't know whether these pins are brought out to
the DSK daughtercard connector -- you have to study the DSK board schematics. If not, then maybe you can find a PDT
test point on the DSK board and run a wire to an unused pin on the daughtercard connector (or redefine an existing
pin). Hopefully the PDT pin is not "NC" and thus buried under the chip :-(
-Jeff
> On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower wrote:
>
>> Varun-
>>
>> > Does anyone know what is the interface used to connect the Virtex-5 FPGA
>> and
>> > the the DSK6416 EMIF ?
>> >
>> > I know the connector to be used on the EMIF side is a Samtec TMS
>> > 140-32-S-D-LC but I have no idea about interfacing that with the
>> Virtex-5.
>> >
>> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't the
>> > same.
>>
>> A couple of initial questions / comments:
>>
>> 1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM?
>> What type of cable are you using?
>>
>> 2) Suggest to post to the group a two-column signal table, one column for
>> EMIF and other for V5 EVM, like this:
>>
>> DSK6461 EMIF Virtex-5 EVM
>> ------------ ------------
>> AWE
>> CEn
>> ARDY
>> A2-Am Ai-Aj
>> D0-Dk D0-Dk
>>
>> where n, m, and i,j,k are to be determined, the objective being to define
>> signal equivalence and connectivity. There
>> is no point to worry about number of pins without first carefully
>> considering the underlying design.
>>
>> -Jeff
>
> --
> Varun
_____________________________________
> First of all, apologies for the really late reply as I fell sick.
>
> I have posted my replies with *.*
>
> A couple of initial questions / comments:
>
> 1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM?
> What type of cable are you using?
>
> *: Less than 4 inches. Since we are going to stack the DSP and FIFO one
> above the other in order to reduce the cable length.*
>
> 2) Suggest to post to the group a two-column signal table, one column for
> EMIF and other for V5 EVM, like this:
>
> * Since some glue logic is required I have pasted the image below that
> describes the connectivity between the FPGA and the EMIF.*
>
> As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
>
> [image: fifo2emif.bmp]
>
> But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the SDRAM
> of the DSK 6416. This means that I need to perform a Peripheral Device
> Transfer(PDT). Perform a PDT involves a different kind of interfacing.
>
> [image: PDT.JPG]
>
> *When I looked up the DSK 6416 datasheet, I can't look up for the PDT pin on
> the EMIF A. Is the PDT pin an internal pin ??*
/APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't know whether these pins are brought out to
the DSK daughtercard connector -- you have to study the DSK board schematics. If not, then maybe you can find a PDT
test point on the DSK board and run a wire to an unused pin on the daughtercard connector (or redefine an existing
pin). Hopefully the PDT pin is not "NC" and thus buried under the chip :-(
-Jeff
> On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower wrote:
>
>> Varun-
>>
>> > Does anyone know what is the interface used to connect the Virtex-5 FPGA
>> and
>> > the the DSK6416 EMIF ?
>> >
>> > I know the connector to be used on the EMIF side is a Samtec TMS
>> > 140-32-S-D-LC but I have no idea about interfacing that with the
>> Virtex-5.
>> >
>> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't the
>> > same.
>>
>> A couple of initial questions / comments:
>>
>> 1) How long do you plan to make the cable between DSK6416 and Virtex-5 EVM?
>> What type of cable are you using?
>>
>> 2) Suggest to post to the group a two-column signal table, one column for
>> EMIF and other for V5 EVM, like this:
>>
>> DSK6461 EMIF Virtex-5 EVM
>> ------------ ------------
>> AWE
>> CEn
>> ARDY
>> A2-Am Ai-Aj
>> D0-Dk D0-Dk
>>
>> where n, m, and i,j,k are to be determined, the objective being to define
>> signal equivalence and connectivity. There
>> is no point to worry about number of pins without first carefully
>> considering the underlying design.
>>
>> -Jeff
>
> --
> Varun
_____________________________________
Reply by ●August 18, 20102010-08-18
Dear Mr.Bower,
Thank you. I just found out the PDT pins. They are actually muxed with the
EMIF A's EA 19 address pin once the PDT Control Register has been
appropriately set.
Can you feed the FIFO status signals to the interrupt pins of the DSK ?
What do you think about the interface between the DSK and FPGA ? I bought
the necessary connectors and cables. I think the only solution is to solder
them first before actually building a board.
Thanks,
On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower wrote:
> Varoonian-
>
> > First of all, apologies for the really late reply as I fell sick.
> >
> > I have posted my replies with *.*
> >
> > A couple of initial questions / comments:
> >
> > 1) How long do you plan to make the cable between DSK6416 and Virtex-5
> EVM?
> > What type of cable are you using?
> >
> > *: Less than 4 inches. Since we are going to stack the DSP and FIFO
> one
> > above the other in order to reduce the cable length.*
> >
> > 2) Suggest to post to the group a two-column signal table, one column for
> > EMIF and other for V5 EVM, like this:
> >
> > * Since some glue logic is required I have pasted the image below that
> > describes the connectivity between the FPGA and the EMIF.*
> >
> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
> >
> > [image: fifo2emif.bmp]
> >
> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the
> SDRAM
> > of the DSK 6416. This means that I need to perform a Peripheral Device
> > Transfer(PDT). Perform a PDT involves a different kind of interfacing.
> >
> > [image: PDT.JPG]
> >
> > *When I looked up the DSK 6416 datasheet, I can't look up for the PDT pin
> on
> > the EMIF A. Is the PDT pin an internal pin ??*
>
> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't
> know whether these pins are brought out to
> the DSK daughtercard connector -- you have to study the DSK board
> schematics. If not, then maybe you can find a PDT
> test point on the DSK board and run a wire to an unused pin on the
> daughtercard connector (or redefine an existing
> pin). Hopefully the PDT pin is not "NC" and thus buried under the chip :-(
>
> -Jeff
>
> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower
> wrote:
> >
> >> Varun-
> >>
> >> > Does anyone know what is the interface used to connect the Virtex-5
> FPGA
> >> and
> >> > the the DSK6416 EMIF ?
> >> >
> >> > I know the connector to be used on the EMIF side is a Samtec TMS
> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
> >> Virtex-5.
> >> >
> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't
> the
> >> > same.
> >>
> >> A couple of initial questions / comments:
> >>
> >> 1) How long do you plan to make the cable between DSK6416 and Virtex-5
> EVM?
> >> What type of cable are you using?
> >>
> >> 2) Suggest to post to the group a two-column signal table, one column
> for
> >> EMIF and other for V5 EVM, like this:
> >>
> >> DSK6461 EMIF Virtex-5 EVM
> >> ------------ ------------
> >> AWE
> >> CEn
> >> ARDY
> >> A2-Am Ai-Aj
> >> D0-Dk D0-Dk
> >>
> >> where n, m, and i,j,k are to be determined, the objective being to
> define
> >> signal equivalence and connectivity. There
> >> is no point to worry about number of pins without first carefully
> >> considering the underlying design.
> >>
> >> -Jeff
> >
> > --
> > Varun
--
Varun
Thank you. I just found out the PDT pins. They are actually muxed with the
EMIF A's EA 19 address pin once the PDT Control Register has been
appropriately set.
Can you feed the FIFO status signals to the interrupt pins of the DSK ?
What do you think about the interface between the DSK and FPGA ? I bought
the necessary connectors and cables. I think the only solution is to solder
them first before actually building a board.
Thanks,
On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower wrote:
> Varoonian-
>
> > First of all, apologies for the really late reply as I fell sick.
> >
> > I have posted my replies with *.*
> >
> > A couple of initial questions / comments:
> >
> > 1) How long do you plan to make the cable between DSK6416 and Virtex-5
> EVM?
> > What type of cable are you using?
> >
> > *: Less than 4 inches. Since we are going to stack the DSP and FIFO
> one
> > above the other in order to reduce the cable length.*
> >
> > 2) Suggest to post to the group a two-column signal table, one column for
> > EMIF and other for V5 EVM, like this:
> >
> > * Since some glue logic is required I have pasted the image below that
> > describes the connectivity between the FPGA and the EMIF.*
> >
> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
> >
> > [image: fifo2emif.bmp]
> >
> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the
> SDRAM
> > of the DSK 6416. This means that I need to perform a Peripheral Device
> > Transfer(PDT). Perform a PDT involves a different kind of interfacing.
> >
> > [image: PDT.JPG]
> >
> > *When I looked up the DSK 6416 datasheet, I can't look up for the PDT pin
> on
> > the EMIF A. Is the PDT pin an internal pin ??*
>
> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't
> know whether these pins are brought out to
> the DSK daughtercard connector -- you have to study the DSK board
> schematics. If not, then maybe you can find a PDT
> test point on the DSK board and run a wire to an unused pin on the
> daughtercard connector (or redefine an existing
> pin). Hopefully the PDT pin is not "NC" and thus buried under the chip :-(
>
> -Jeff
>
> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower
> wrote:
> >
> >> Varun-
> >>
> >> > Does anyone know what is the interface used to connect the Virtex-5
> FPGA
> >> and
> >> > the the DSK6416 EMIF ?
> >> >
> >> > I know the connector to be used on the EMIF side is a Samtec TMS
> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
> >> Virtex-5.
> >> >
> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't
> the
> >> > same.
> >>
> >> A couple of initial questions / comments:
> >>
> >> 1) How long do you plan to make the cable between DSK6416 and Virtex-5
> EVM?
> >> What type of cable are you using?
> >>
> >> 2) Suggest to post to the group a two-column signal table, one column
> for
> >> EMIF and other for V5 EVM, like this:
> >>
> >> DSK6461 EMIF Virtex-5 EVM
> >> ------------ ------------
> >> AWE
> >> CEn
> >> ARDY
> >> A2-Am Ai-Aj
> >> D0-Dk D0-Dk
> >>
> >> where n, m, and i,j,k are to be determined, the objective being to
> define
> >> signal equivalence and connectivity. There
> >> is no point to worry about number of pins without first carefully
> >> considering the underlying design.
> >>
> >> -Jeff
> >
> > --
> > Varun
--
Varun
Reply by ●August 19, 20102010-08-19
Varoonian-
> Thank you. I just found out the PDT pins. They are actually muxed with the
> EMIF A's EA 19 address pin once the PDT Control Register has been
> appropriately set.
>
> Can you feed the FIFO status signals to the interrupt pins of the DSK ?
Not sure. Since the DSP controls all SDRAM read/write (acting as "DMA engine", to use Xilinx terminology), and Xilinx
doesn't show FIFO status signals (full, empty, etc) connected in any way, then I would assume that Xilinx expects the
"other side" of the FIFO logic to always be slower (on average) than the SDRAM. For example, if initial SDRAM access
is slow and the FIFO fills up a little, then subsequent (consecutive) accesses are fast and the FIFO will unwind.
Could the FIFO completely fill up? Good question, depends a lot on your side of the FIFO. Suggest to ask Xilinx FAE
about this.
A question for your design: why do you need to know FIFO status? If you're writing DSP code to control DMA activity,
then your code can receive a 'DMA done' interrupt to know when the DMA transfer is complete.
> What do you think about the interface between the DSK and FPGA ? I bought
> the necessary connectors and cables. I think the only solution is to solder
> them first before actually building a board.
The cables should not solder to anything, they should crimp to connectors that match the board receptacles. Do you
mean that since the connectors are not the same width, then you need an adapter card at one end? And this requires
soldering? Otherwise I don't get you. What connectors and cables do you have? Maybe you can post a picture.
-Jeff
> On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower wrote:
>
>> Varoonian-
>>
>> > First of all, apologies for the really late reply as I fell sick.
>> >
>> > I have posted my replies with *.*
>> >
>> > A couple of initial questions / comments:
>> >
>> > 1) How long do you plan to make the cable between DSK6416 and Virtex-5
>> EVM?
>> > What type of cable are you using?
>> >
>> > *: Less than 4 inches. Since we are going to stack the DSP and FIFO
>> one
>> > above the other in order to reduce the cable length.*
>> >
>> > 2) Suggest to post to the group a two-column signal table, one column for
>> > EMIF and other for V5 EVM, like this:
>> >
>> > * Since some glue logic is required I have pasted the image below that
>> > describes the connectivity between the FPGA and the EMIF.*
>> >
>> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
>> >
>> > [image: fifo2emif.bmp]
>> >
>> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the
>> SDRAM
>> > of the DSK 6416. This means that I need to perform a Peripheral Device
>> > Transfer(PDT). Perform a PDT involves a different kind of interfacing.
>> >
>> > [image: PDT.JPG]
>> >
>> > *When I looked up the DSK 6416 datasheet, I can't look up for the PDT pin
>> on
>> > the EMIF A. Is the PDT pin an internal pin ??*
>>
>> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't
>> know whether these pins are brought out to
>> the DSK daughtercard connector -- you have to study the DSK board
>> schematics. If not, then maybe you can find a PDT
>> test point on the DSK board and run a wire to an unused pin on the
>> daughtercard connector (or redefine an existing
>> pin). Hopefully the PDT pin is not "NC" and thus buried under the chip :-(
>>
>> -Jeff
>>
>> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower
>> wrote:
>> >
>> >> Varun-
>> >>
>> >> > Does anyone know what is the interface used to connect the Virtex-5
>> FPGA
>> >> and
>> >> > the the DSK6416 EMIF ?
>> >> >
>> >> > I know the connector to be used on the EMIF side is a Samtec TMS
>> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
>> >> Virtex-5.
>> >> >
>> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't
>> the
>> >> > same.
>> >>
>> >> A couple of initial questions / comments:
>> >>
>> >> 1) How long do you plan to make the cable between DSK6416 and Virtex-5
>> EVM?
>> >> What type of cable are you using?
>> >>
>> >> 2) Suggest to post to the group a two-column signal table, one column
>> for
>> >> EMIF and other for V5 EVM, like this:
>> >>
>> >> DSK6461 EMIF Virtex-5 EVM
>> >> ------------ ------------
>> >> AWE
>> >> CEn
>> >> ARDY
>> >> A2-Am Ai-Aj
>> >> D0-Dk D0-Dk
>> >>
>> >> where n, m, and i,j,k are to be determined, the objective being to
>> define
>> >> signal equivalence and connectivity. There
>> >> is no point to worry about number of pins without first carefully
>> >> considering the underlying design.
>> >>
>> >> -Jeff
>> >
>> > --
>> > Varun
> --
> Varun
_____________________________________
> Thank you. I just found out the PDT pins. They are actually muxed with the
> EMIF A's EA 19 address pin once the PDT Control Register has been
> appropriately set.
>
> Can you feed the FIFO status signals to the interrupt pins of the DSK ?
Not sure. Since the DSP controls all SDRAM read/write (acting as "DMA engine", to use Xilinx terminology), and Xilinx
doesn't show FIFO status signals (full, empty, etc) connected in any way, then I would assume that Xilinx expects the
"other side" of the FIFO logic to always be slower (on average) than the SDRAM. For example, if initial SDRAM access
is slow and the FIFO fills up a little, then subsequent (consecutive) accesses are fast and the FIFO will unwind.
Could the FIFO completely fill up? Good question, depends a lot on your side of the FIFO. Suggest to ask Xilinx FAE
about this.
A question for your design: why do you need to know FIFO status? If you're writing DSP code to control DMA activity,
then your code can receive a 'DMA done' interrupt to know when the DMA transfer is complete.
> What do you think about the interface between the DSK and FPGA ? I bought
> the necessary connectors and cables. I think the only solution is to solder
> them first before actually building a board.
The cables should not solder to anything, they should crimp to connectors that match the board receptacles. Do you
mean that since the connectors are not the same width, then you need an adapter card at one end? And this requires
soldering? Otherwise I don't get you. What connectors and cables do you have? Maybe you can post a picture.
-Jeff
> On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower wrote:
>
>> Varoonian-
>>
>> > First of all, apologies for the really late reply as I fell sick.
>> >
>> > I have posted my replies with *.*
>> >
>> > A couple of initial questions / comments:
>> >
>> > 1) How long do you plan to make the cable between DSK6416 and Virtex-5
>> EVM?
>> > What type of cable are you using?
>> >
>> > *: Less than 4 inches. Since we are going to stack the DSP and FIFO
>> one
>> > above the other in order to reduce the cable length.*
>> >
>> > 2) Suggest to post to the group a two-column signal table, one column for
>> > EMIF and other for V5 EVM, like this:
>> >
>> > * Since some glue logic is required I have pasted the image below that
>> > describes the connectivity between the FPGA and the EMIF.*
>> >
>> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
>> >
>> > [image: fifo2emif.bmp]
>> >
>> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the
>> SDRAM
>> > of the DSK 6416. This means that I need to perform a Peripheral Device
>> > Transfer(PDT). Perform a PDT involves a different kind of interfacing.
>> >
>> > [image: PDT.JPG]
>> >
>> > *When I looked up the DSK 6416 datasheet, I can't look up for the PDT pin
>> on
>> > the EMIF A. Is the PDT pin an internal pin ??*
>>
>> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't
>> know whether these pins are brought out to
>> the DSK daughtercard connector -- you have to study the DSK board
>> schematics. If not, then maybe you can find a PDT
>> test point on the DSK board and run a wire to an unused pin on the
>> daughtercard connector (or redefine an existing
>> pin). Hopefully the PDT pin is not "NC" and thus buried under the chip :-(
>>
>> -Jeff
>>
>> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower
>> wrote:
>> >
>> >> Varun-
>> >>
>> >> > Does anyone know what is the interface used to connect the Virtex-5
>> FPGA
>> >> and
>> >> > the the DSK6416 EMIF ?
>> >> >
>> >> > I know the connector to be used on the EMIF side is a Samtec TMS
>> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
>> >> Virtex-5.
>> >> >
>> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM aren't
>> the
>> >> > same.
>> >>
>> >> A couple of initial questions / comments:
>> >>
>> >> 1) How long do you plan to make the cable between DSK6416 and Virtex-5
>> EVM?
>> >> What type of cable are you using?
>> >>
>> >> 2) Suggest to post to the group a two-column signal table, one column
>> for
>> >> EMIF and other for V5 EVM, like this:
>> >>
>> >> DSK6461 EMIF Virtex-5 EVM
>> >> ------------ ------------
>> >> AWE
>> >> CEn
>> >> ARDY
>> >> A2-Am Ai-Aj
>> >> D0-Dk D0-Dk
>> >>
>> >> where n, m, and i,j,k are to be determined, the objective being to
>> define
>> >> signal equivalence and connectivity. There
>> >> is no point to worry about number of pins without first carefully
>> >> considering the underlying design.
>> >>
>> >> -Jeff
>> >
>> > --
>> > Varun
> --
> Varun
_____________________________________
Reply by ●August 19, 20102010-08-19
Varun-
>> Varoonian-
>>
>> > Thank you. I just found out the PDT pins. They are actually muxed with
>> the
>> > EMIF A's EA 19 address pin once the PDT Control Register has been
>> > appropriately set.
>> >
>> > Can you feed the FIFO status signals to the interrupt pins of the DSK ?
>>
>> Not sure. Since the DSP controls all SDRAM read/write (acting as "DMA
>> engine", to use Xilinx terminology), and Xilinx
>> doesn't show FIFO status signals (full, empty, etc) connected in any way,
>> then I would assume that Xilinx expects the
>> "other side" of the FIFO logic to always be slower (on average) than the
>> SDRAM. For example, if initial SDRAM access
>> is slow and the FIFO fills up a little, then subsequent (consecutive)
>> accesses are fast and the FIFO will unwind.
>>
>> Could the FIFO completely fill up? Good question, depends a lot on your
>> side of the FIFO. Suggest to ask Xilinx FAE
>> about this.
>>
>> A question for your design: why do you need to know FIFO status? If
>> you're writing DSP code to control DMA activity,
>> then your code can receive a 'DMA done' interrupt to know when the DMA
>> transfer is complete.
>> * IN my project an ADC at 200 MHz sends 8 bit differential LVDS to the
> FIFO(FPGA) which is in turn read (32 bit ) by the DSP at the EMIF CLK
> frequency (120 MHz) and stored in the SDRAM. So I am gonna do PDT.
>
> Since I am doing DMA for the first time I am not very well versed in this
> yet. If the FIFO becomes empty, the DSP needs to be intimated to stop the
> READ.
For a continuous stream of incoming data the typical method is double buffering (in your case, maybe split the FIFO in
half, or have 2 FIFOs). When each buffer is full the DSP is notified and starts a DMA transfer, while input streaming
continues in the other buffer. The buffer transfers toggle back and forth. To implement this, your FPGA would issue
some type of "buffer full" interrupt. If Xilinx hasn't defined a signal for this then hopefully there is an unused
pin you can use.
>> > What do you think about the interface between the DSK and FPGA ? I bought
>> > the necessary connectors and cables. I think the only solution is to
>> solder
>> > them first before actually building a board.
>>
>> The cables should not solder to anything, they should crimp to connectors
>> that match the board receptacles. Do you
>> mean that since the connectors are not the same width, then you need an
>> adapter card at one end? And this requires
>> soldering? Otherwise I don't get you. What connectors and cables do you
>> have? Maybe you can post a picture.
>
> * regarding the cables. TI DSP have 0.05 inch pitch for their connectors
> whereas Xilinx connectors have 0.1 inch pitch connectors.
>
> These two do not mate, nor is any connector available. So for testing
> purposes I cannot straight away build a board. Therefore I need to solder
> cables from both connectors initially. If that works fine then I will build
> a board.
My guess is a hand-soldered 4" cable is going to be problematic for your project -- 120 MHz clock and data transfers
are probably going to get smushed. You might look into Mictor type of cables (individually shielded conductors);
these are used for logic analyzers. Another idea would be to use LVDS-supported pins on the Virtex5 EVM board and
make (or purchase) a daughtercard for the DSK board that has LVDS transceivers and an appropriate connector. I
suggest that you do some serious digging on this, and ask for advice both on Xilinx forum and TI e2e forum.
-Jeff
>> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower
>> wrote:
>> >
>> >> Varoonian-
>> >>
>> >> > First of all, apologies for the really late reply as I fell sick.
>> >> >
>> >> > I have posted my replies with *.*
>> >> >
>> >> > A couple of initial questions / comments:
>> >> >
>> >> > 1) How long do you plan to make the cable between DSK6416 and Virtex-5
>> >> EVM?
>> >> > What type of cable are you using?
>> >> >
>> >> > *: Less than 4 inches. Since we are going to stack the DSP and FIFO
>> >> one
>> >> > above the other in order to reduce the cable length.*
>> >> >
>> >> > 2) Suggest to post to the group a two-column signal table, one column
>> for
>> >> > EMIF and other for V5 EVM, like this:
>> >> >
>> >> > * Since some glue logic is required I have pasted the image below
>> that
>> >> > describes the connectivity between the FPGA and the EMIF.*
>> >> >
>> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
>> >> >
>> >> > [image: fifo2emif.bmp]
>> >> >
>> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the
>> >> SDRAM
>> >> > of the DSK 6416. This means that I need to perform a Peripheral Device
>> >> > Transfer(PDT). Perform a PDT involves a different kind of interfacing.
>> >> >
>> >> > [image: PDT.JPG]
>> >> >
>> >> > *When I looked up the DSK 6416 datasheet, I can't look up for the PDT
>> pin
>> >> on
>> >> > the EMIF A. Is the PDT pin an internal pin ??*
>> >>
>> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't
>> >> know whether these pins are brought out to
>> >> the DSK daughtercard connector -- you have to study the DSK board
>> >> schematics. If not, then maybe you can find a PDT
>> >> test point on the DSK board and run a wire to an unused pin on the
>> >> daughtercard connector (or redefine an existing
>> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the chip
>> :-(
>> >>
>> >> -Jeff
>> >>
>> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower
>> >> wrote:
>> >> >
>> >> >> Varun-
>> >> >>
>> >> >> > Does anyone know what is the interface used to connect the Virtex-5
>> >> FPGA
>> >> >> and
>> >> >> > the the DSK6416 EMIF ?
>> >> >> >
>> >> >> > I know the connector to be used on the EMIF side is a Samtec TMS
>> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
>> >> >> Virtex-5.
>> >> >> >
>> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM
>> aren't
>> >> the
>> >> >> > same.
>> >> >>
>> >> >> A couple of initial questions / comments:
>> >> >>
>> >> >> 1) How long do you plan to make the cable between DSK6416 and
>> Virtex-5
>> >> EVM?
>> >> >> What type of cable are you using?
>> >> >>
>> >> >> 2) Suggest to post to the group a two-column signal table, one column
>> >> for
>> >> >> EMIF and other for V5 EVM, like this:
>> >> >>
>> >> >> DSK6461 EMIF Virtex-5 EVM
>> >> >> ------------ ------------
>> >> >> AWE
>> >> >> CEn
>> >> >> ARDY
>> >> >> A2-Am Ai-Aj
>> >> >> D0-Dk D0-Dk
>> >> >>
>> >> >> where n, m, and i,j,k are to be determined, the objective being to
>> >> define
>> >> >> signal equivalence and connectivity. There
>> >> >> is no point to worry about number of pins without first carefully
>> >> >> considering the underlying design.
>> >> >>
>> >> >> -Jeff
_____________________________________
>> Varoonian-
>>
>> > Thank you. I just found out the PDT pins. They are actually muxed with
>> the
>> > EMIF A's EA 19 address pin once the PDT Control Register has been
>> > appropriately set.
>> >
>> > Can you feed the FIFO status signals to the interrupt pins of the DSK ?
>>
>> Not sure. Since the DSP controls all SDRAM read/write (acting as "DMA
>> engine", to use Xilinx terminology), and Xilinx
>> doesn't show FIFO status signals (full, empty, etc) connected in any way,
>> then I would assume that Xilinx expects the
>> "other side" of the FIFO logic to always be slower (on average) than the
>> SDRAM. For example, if initial SDRAM access
>> is slow and the FIFO fills up a little, then subsequent (consecutive)
>> accesses are fast and the FIFO will unwind.
>>
>> Could the FIFO completely fill up? Good question, depends a lot on your
>> side of the FIFO. Suggest to ask Xilinx FAE
>> about this.
>>
>> A question for your design: why do you need to know FIFO status? If
>> you're writing DSP code to control DMA activity,
>> then your code can receive a 'DMA done' interrupt to know when the DMA
>> transfer is complete.
>> * IN my project an ADC at 200 MHz sends 8 bit differential LVDS to the
> FIFO(FPGA) which is in turn read (32 bit ) by the DSP at the EMIF CLK
> frequency (120 MHz) and stored in the SDRAM. So I am gonna do PDT.
>
> Since I am doing DMA for the first time I am not very well versed in this
> yet. If the FIFO becomes empty, the DSP needs to be intimated to stop the
> READ.
For a continuous stream of incoming data the typical method is double buffering (in your case, maybe split the FIFO in
half, or have 2 FIFOs). When each buffer is full the DSP is notified and starts a DMA transfer, while input streaming
continues in the other buffer. The buffer transfers toggle back and forth. To implement this, your FPGA would issue
some type of "buffer full" interrupt. If Xilinx hasn't defined a signal for this then hopefully there is an unused
pin you can use.
>> > What do you think about the interface between the DSK and FPGA ? I bought
>> > the necessary connectors and cables. I think the only solution is to
>> solder
>> > them first before actually building a board.
>>
>> The cables should not solder to anything, they should crimp to connectors
>> that match the board receptacles. Do you
>> mean that since the connectors are not the same width, then you need an
>> adapter card at one end? And this requires
>> soldering? Otherwise I don't get you. What connectors and cables do you
>> have? Maybe you can post a picture.
>
> * regarding the cables. TI DSP have 0.05 inch pitch for their connectors
> whereas Xilinx connectors have 0.1 inch pitch connectors.
>
> These two do not mate, nor is any connector available. So for testing
> purposes I cannot straight away build a board. Therefore I need to solder
> cables from both connectors initially. If that works fine then I will build
> a board.
My guess is a hand-soldered 4" cable is going to be problematic for your project -- 120 MHz clock and data transfers
are probably going to get smushed. You might look into Mictor type of cables (individually shielded conductors);
these are used for logic analyzers. Another idea would be to use LVDS-supported pins on the Virtex5 EVM board and
make (or purchase) a daughtercard for the DSK board that has LVDS transceivers and an appropriate connector. I
suggest that you do some serious digging on this, and ask for advice both on Xilinx forum and TI e2e forum.
-Jeff
>> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower
>> wrote:
>> >
>> >> Varoonian-
>> >>
>> >> > First of all, apologies for the really late reply as I fell sick.
>> >> >
>> >> > I have posted my replies with *.*
>> >> >
>> >> > A couple of initial questions / comments:
>> >> >
>> >> > 1) How long do you plan to make the cable between DSK6416 and Virtex-5
>> >> EVM?
>> >> > What type of cable are you using?
>> >> >
>> >> > *: Less than 4 inches. Since we are going to stack the DSP and FIFO
>> >> one
>> >> > above the other in order to reduce the cable length.*
>> >> >
>> >> > 2) Suggest to post to the group a two-column signal table, one column
>> for
>> >> > EMIF and other for V5 EVM, like this:
>> >> >
>> >> > * Since some glue logic is required I have pasted the image below
>> that
>> >> > describes the connectivity between the FPGA and the EMIF.*
>> >> >
>> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
>> >> >
>> >> > [image: fifo2emif.bmp]
>> >> >
>> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the
>> >> SDRAM
>> >> > of the DSK 6416. This means that I need to perform a Peripheral Device
>> >> > Transfer(PDT). Perform a PDT involves a different kind of interfacing.
>> >> >
>> >> > [image: PDT.JPG]
>> >> >
>> >> > *When I looked up the DSK 6416 datasheet, I can't look up for the PDT
>> pin
>> >> on
>> >> > the EMIF A. Is the PDT pin an internal pin ??*
>> >>
>> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't
>> >> know whether these pins are brought out to
>> >> the DSK daughtercard connector -- you have to study the DSK board
>> >> schematics. If not, then maybe you can find a PDT
>> >> test point on the DSK board and run a wire to an unused pin on the
>> >> daughtercard connector (or redefine an existing
>> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the chip
>> :-(
>> >>
>> >> -Jeff
>> >>
>> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower
>> >> wrote:
>> >> >
>> >> >> Varun-
>> >> >>
>> >> >> > Does anyone know what is the interface used to connect the Virtex-5
>> >> FPGA
>> >> >> and
>> >> >> > the the DSK6416 EMIF ?
>> >> >> >
>> >> >> > I know the connector to be used on the EMIF side is a Samtec TMS
>> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
>> >> >> Virtex-5.
>> >> >> >
>> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM
>> aren't
>> >> the
>> >> >> > same.
>> >> >>
>> >> >> A couple of initial questions / comments:
>> >> >>
>> >> >> 1) How long do you plan to make the cable between DSK6416 and
>> Virtex-5
>> >> EVM?
>> >> >> What type of cable are you using?
>> >> >>
>> >> >> 2) Suggest to post to the group a two-column signal table, one column
>> >> for
>> >> >> EMIF and other for V5 EVM, like this:
>> >> >>
>> >> >> DSK6461 EMIF Virtex-5 EVM
>> >> >> ------------ ------------
>> >> >> AWE
>> >> >> CEn
>> >> >> ARDY
>> >> >> A2-Am Ai-Aj
>> >> >> D0-Dk D0-Dk
>> >> >>
>> >> >> where n, m, and i,j,k are to be determined, the objective being to
>> >> define
>> >> >> signal equivalence and connectivity. There
>> >> >> is no point to worry about number of pins without first carefully
>> >> >> considering the underlying design.
>> >> >>
>> >> >> -Jeff
_____________________________________
Reply by ●August 19, 20102010-08-19
On Thu, Aug 19, 2010 at 10:14 AM, Jeff Brower wrote:
> Varun-
> For a continuous stream of incoming data the typical method is double
> buffering (in your case, maybe split the FIFO in
> half, or have 2 FIFOs). When each buffer is full the DSP is notified and
> starts a DMA transfer, while input streaming
> continues in the other buffer. The buffer transfers toggle back and forth.
> To implement this, your FPGA would issue
> some type of "buffer full" interrupt. If Xilinx hasn't defined a signal
> for this then hopefully there is an unused
> pin you can use.
>
> * So two FIFO's connected back to back. The one near the DSP bursts out
> data when it is FULL.* Is that correct ? *The FIFO does have a FIFO full
> signal and empty signal. Can you suggest any literature on this ?
> *
>
My guess is a hand-soldered 4" cable is going to be problematic for your
> project -- 120 MHz clock and data transfers
> are probably going to get smushed. You might look into Mictor type of
> cables (individually shielded conductors);
> these are used for logic analyzers. Another idea would be to use
> LVDS-supported pins on the Virtex5 EVM board and
> make (or purchase) a daughtercard for the DSK board that has LVDS
> transceivers and an appropriate connector. I
> suggest that you do some serious digging on this, and ask for advice both
> on Xilinx forum and TI e2e forum.
>
* I agree. Xilinx FPGA does have pins which support LVDS. I * checked out
*MICTOR ( ones mfg by signalogic too. ) I am very skeptical whether I would
be able to get* MICTORs that could mate with the Xilinx 0.05 inch headers. I
will have a look. Thanks a lot for your inputs Mr.Bower.
Thanks,
>
> -Jeff
>
> >> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower
> >> wrote:
> >> >
> >> >> Varoonian-
> >> >>
> >> >> > First of all, apologies for the really late reply as I fell sick.
> >> >> >
> >> >> > I have posted my replies with *.*
> >> >> >
> >> >> > A couple of initial questions / comments:
> >> >> >
> >> >> > 1) How long do you plan to make the cable between DSK6416 and
> Virtex-5
> >> >> EVM?
> >> >> > What type of cable are you using?
> >> >> >
> >> >> > *: Less than 4 inches. Since we are going to stack the DSP and
> FIFO
> >> >> one
> >> >> > above the other in order to reduce the cable length.*
> >> >> >
> >> >> > 2) Suggest to post to the group a two-column signal table, one
> column
> >> for
> >> >> > EMIF and other for V5 EVM, like this:
> >> >> >
> >> >> > * Since some glue logic is required I have pasted the image
> below
> >> that
> >> >> > describes the connectivity between the FPGA and the EMIF.*
> >> >> >
> >> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF
> are
> >> >> >
> >> >> > [image: fifo2emif.bmp]
> >> >> >
> >> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in
> the
> >> >> SDRAM
> >> >> > of the DSK 6416. This means that I need to perform a Peripheral
> Device
> >> >> > Transfer(PDT). Perform a PDT involves a different kind of
> interfacing.
> >> >> >
> >> >> > [image: PDT.JPG]
> >> >> >
> >> >> > *When I looked up the DSK 6416 datasheet, I can't look up for the
> PDT
> >> pin
> >> >> on
> >> >> > the EMIF A. Is the PDT pin an internal pin ??*
> >> >>
> >> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I
> don't
> >> >> know whether these pins are brought out to
> >> >> the DSK daughtercard connector -- you have to study the DSK board
> >> >> schematics. If not, then maybe you can find a PDT
> >> >> test point on the DSK board and run a wire to an unused pin on the
> >> >> daughtercard connector (or redefine an existing
> >> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the
> chip
> >> :-(
> >> >>
> >> >> -Jeff
> >> >>
> >> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower <
> j...@signalogic.com>
> >> >> wrote:
> >> >> >
> >> >> >> Varun-
> >> >> >>
> >> >> >> > Does anyone know what is the interface used to connect the
> Virtex-5
> >> >> FPGA
> >> >> >> and
> >> >> >> > the the DSK6416 EMIF ?
> >> >> >> >
> >> >> >> > I know the connector to be used on the EMIF side is a Samtec TMS
> >> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
> >> >> >> Virtex-5.
> >> >> >> >
> >> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM
> >> aren't
> >> >> the
> >> >> >> > same.
> >> >> >>
> >> >> >> A couple of initial questions / comments:
> >> >> >>
> >> >> >> 1) How long do you plan to make the cable between DSK6416 and
> >> Virtex-5
> >> >> EVM?
> >> >> >> What type of cable are you using?
> >> >> >>
> >> >> >> 2) Suggest to post to the group a two-column signal table, one
> column
> >> >> for
> >> >> >> EMIF and other for V5 EVM, like this:
> >> >> >>
> >> >> >> DSK6461 EMIF Virtex-5 EVM
> >> >> >> ------------ ------------
> >> >> >> AWE
> >> >> >> CEn
> >> >> >> ARDY
> >> >> >> A2-Am Ai-Aj
> >> >> >> D0-Dk D0-Dk
> >> >> >>
> >> >> >> where n, m, and i,j,k are to be determined, the objective being to
> >> >> define
> >> >> >> signal equivalence and connectivity. There
> >> >> >> is no point to worry about number of pins without first carefully
> >> >> >> considering the underlying design.
> >> >> >>
> >> >> >> -Jeff
--
Varun
> Varun-
> For a continuous stream of incoming data the typical method is double
> buffering (in your case, maybe split the FIFO in
> half, or have 2 FIFOs). When each buffer is full the DSP is notified and
> starts a DMA transfer, while input streaming
> continues in the other buffer. The buffer transfers toggle back and forth.
> To implement this, your FPGA would issue
> some type of "buffer full" interrupt. If Xilinx hasn't defined a signal
> for this then hopefully there is an unused
> pin you can use.
>
> * So two FIFO's connected back to back. The one near the DSP bursts out
> data when it is FULL.* Is that correct ? *The FIFO does have a FIFO full
> signal and empty signal. Can you suggest any literature on this ?
> *
>
My guess is a hand-soldered 4" cable is going to be problematic for your
> project -- 120 MHz clock and data transfers
> are probably going to get smushed. You might look into Mictor type of
> cables (individually shielded conductors);
> these are used for logic analyzers. Another idea would be to use
> LVDS-supported pins on the Virtex5 EVM board and
> make (or purchase) a daughtercard for the DSK board that has LVDS
> transceivers and an appropriate connector. I
> suggest that you do some serious digging on this, and ask for advice both
> on Xilinx forum and TI e2e forum.
>
* I agree. Xilinx FPGA does have pins which support LVDS. I * checked out
*MICTOR ( ones mfg by signalogic too. ) I am very skeptical whether I would
be able to get* MICTORs that could mate with the Xilinx 0.05 inch headers. I
will have a look. Thanks a lot for your inputs Mr.Bower.
Thanks,
>
> -Jeff
>
> >> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower
> >> wrote:
> >> >
> >> >> Varoonian-
> >> >>
> >> >> > First of all, apologies for the really late reply as I fell sick.
> >> >> >
> >> >> > I have posted my replies with *.*
> >> >> >
> >> >> > A couple of initial questions / comments:
> >> >> >
> >> >> > 1) How long do you plan to make the cable between DSK6416 and
> Virtex-5
> >> >> EVM?
> >> >> > What type of cable are you using?
> >> >> >
> >> >> > *: Less than 4 inches. Since we are going to stack the DSP and
> FIFO
> >> >> one
> >> >> > above the other in order to reduce the cable length.*
> >> >> >
> >> >> > 2) Suggest to post to the group a two-column signal table, one
> column
> >> for
> >> >> > EMIF and other for V5 EVM, like this:
> >> >> >
> >> >> > * Since some glue logic is required I have pasted the image
> below
> >> that
> >> >> > describes the connectivity between the FPGA and the EMIF.*
> >> >> >
> >> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF
> are
> >> >> >
> >> >> > [image: fifo2emif.bmp]
> >> >> >
> >> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in
> the
> >> >> SDRAM
> >> >> > of the DSK 6416. This means that I need to perform a Peripheral
> Device
> >> >> > Transfer(PDT). Perform a PDT involves a different kind of
> interfacing.
> >> >> >
> >> >> > [image: PDT.JPG]
> >> >> >
> >> >> > *When I looked up the DSK 6416 datasheet, I can't look up for the
> PDT
> >> pin
> >> >> on
> >> >> > the EMIF A. Is the PDT pin an internal pin ??*
> >> >>
> >> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I
> don't
> >> >> know whether these pins are brought out to
> >> >> the DSK daughtercard connector -- you have to study the DSK board
> >> >> schematics. If not, then maybe you can find a PDT
> >> >> test point on the DSK board and run a wire to an unused pin on the
> >> >> daughtercard connector (or redefine an existing
> >> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the
> chip
> >> :-(
> >> >>
> >> >> -Jeff
> >> >>
> >> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower <
> j...@signalogic.com>
> >> >> wrote:
> >> >> >
> >> >> >> Varun-
> >> >> >>
> >> >> >> > Does anyone know what is the interface used to connect the
> Virtex-5
> >> >> FPGA
> >> >> >> and
> >> >> >> > the the DSK6416 EMIF ?
> >> >> >> >
> >> >> >> > I know the connector to be used on the EMIF side is a Samtec TMS
> >> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
> >> >> >> Virtex-5.
> >> >> >> >
> >> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM
> >> aren't
> >> >> the
> >> >> >> > same.
> >> >> >>
> >> >> >> A couple of initial questions / comments:
> >> >> >>
> >> >> >> 1) How long do you plan to make the cable between DSK6416 and
> >> Virtex-5
> >> >> EVM?
> >> >> >> What type of cable are you using?
> >> >> >>
> >> >> >> 2) Suggest to post to the group a two-column signal table, one
> column
> >> >> for
> >> >> >> EMIF and other for V5 EVM, like this:
> >> >> >>
> >> >> >> DSK6461 EMIF Virtex-5 EVM
> >> >> >> ------------ ------------
> >> >> >> AWE
> >> >> >> CEn
> >> >> >> ARDY
> >> >> >> A2-Am Ai-Aj
> >> >> >> D0-Dk D0-Dk
> >> >> >>
> >> >> >> where n, m, and i,j,k are to be determined, the objective being to
> >> >> define
> >> >> >> signal equivalence and connectivity. There
> >> >> >> is no point to worry about number of pins without first carefully
> >> >> >> considering the underlying design.
> >> >> >>
> >> >> >> -Jeff
--
Varun
Reply by ●August 19, 20102010-08-19
Dear Mr.Bowers,
First of all thanks for replying. I interspersed my replies with a * as
usual.*
On Wed, Aug 18, 2010 at 8:52 PM, Jeff Brower wrote:
> Varoonian-
>
> > Thank you. I just found out the PDT pins. They are actually muxed with
> the
> > EMIF A's EA 19 address pin once the PDT Control Register has been
> > appropriately set.
> >
> > Can you feed the FIFO status signals to the interrupt pins of the DSK ?
>
> Not sure. Since the DSP controls all SDRAM read/write (acting as "DMA
> engine", to use Xilinx terminology), and Xilinx
> doesn't show FIFO status signals (full, empty, etc) connected in any way,
> then I would assume that Xilinx expects the
> "other side" of the FIFO logic to always be slower (on average) than the
> SDRAM. For example, if initial SDRAM access
> is slow and the FIFO fills up a little, then subsequent (consecutive)
> accesses are fast and the FIFO will unwind.
>
> Could the FIFO completely fill up? Good question, depends a lot on your
> side of the FIFO. Suggest to ask Xilinx FAE
> about this.
>
> A question for your design: why do you need to know FIFO status? If
> you're writing DSP code to control DMA activity,
> then your code can receive a 'DMA done' interrupt to know when the DMA
> transfer is complete.
>
* IN my project an ADC at 200 MHz sends 8 bit differential LVDS to the
FIFO(FPGA) which is in turn read (32 bit ) by the DSP at the EMIF CLK
frequency (120 MHz) and stored in the SDRAM. So I am gonna do PDT.
Since I am doing DMA for the first time I am not very well versed in this
yet. If the FIFO becomes empty, the DSP needs to be intimated to stop the
READ.
*
>
> > What do you think about the interface between the DSK and FPGA ? I bought
> > the necessary connectors and cables. I think the only solution is to
> solder
> > them first before actually building a board.
>
> The cables should not solder to anything, they should crimp to connectors
> that match the board receptacles. Do you
> mean that since the connectors are not the same width, then you need an
> adapter card at one end? And this requires
> soldering? Otherwise I don't get you. What connectors and cables do you
> have? Maybe you can post a picture.
>
* regarding the cables. TI DSP have 0.05 inch pitch for their connectors
whereas Xilinx connectors have 0.1 inch pitch connectors.
These two do not mate, nor is any connector available. So for testing
purposes I cannot straight away build a board. Therefore I need to solder
cables from both connectors initially. If that works fine then I will build
a board.
*Thanks,
>
> -Jeff
>
> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower
> wrote:
> >
> >> Varoonian-
> >>
> >> > First of all, apologies for the really late reply as I fell sick.
> >> >
> >> > I have posted my replies with *.*
> >> >
> >> > A couple of initial questions / comments:
> >> >
> >> > 1) How long do you plan to make the cable between DSK6416 and Virtex-5
> >> EVM?
> >> > What type of cable are you using?
> >> >
> >> > *: Less than 4 inches. Since we are going to stack the DSP and FIFO
> >> one
> >> > above the other in order to reduce the cable length.*
> >> >
> >> > 2) Suggest to post to the group a two-column signal table, one column
> for
> >> > EMIF and other for V5 EVM, like this:
> >> >
> >> > * Since some glue logic is required I have pasted the image below
> that
> >> > describes the connectivity between the FPGA and the EMIF.*
> >> >
> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
> >> >
> >> > [image: fifo2emif.bmp]
> >> >
> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the
> >> SDRAM
> >> > of the DSK 6416. This means that I need to perform a Peripheral Device
> >> > Transfer(PDT). Perform a PDT involves a different kind of interfacing.
> >> >
> >> > [image: PDT.JPG]
> >> >
> >> > *When I looked up the DSK 6416 datasheet, I can't look up for the PDT
> pin
> >> on
> >> > the EMIF A. Is the PDT pin an internal pin ??*
> >>
> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't
> >> know whether these pins are brought out to
> >> the DSK daughtercard connector -- you have to study the DSK board
> >> schematics. If not, then maybe you can find a PDT
> >> test point on the DSK board and run a wire to an unused pin on the
> >> daughtercard connector (or redefine an existing
> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the chip
> :-(
> >>
> >> -Jeff
> >>
> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower
> >> wrote:
> >> >
> >> >> Varun-
> >> >>
> >> >> > Does anyone know what is the interface used to connect the Virtex-5
> >> FPGA
> >> >> and
> >> >> > the the DSK6416 EMIF ?
> >> >> >
> >> >> > I know the connector to be used on the EMIF side is a Samtec TMS
> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
> >> >> Virtex-5.
> >> >> >
> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM
> aren't
> >> the
> >> >> > same.
> >> >>
> >> >> A couple of initial questions / comments:
> >> >>
> >> >> 1) How long do you plan to make the cable between DSK6416 and
> Virtex-5
> >> EVM?
> >> >> What type of cable are you using?
> >> >>
> >> >> 2) Suggest to post to the group a two-column signal table, one column
> >> for
> >> >> EMIF and other for V5 EVM, like this:
> >> >>
> >> >> DSK6461 EMIF Virtex-5 EVM
> >> >> ------------ ------------
> >> >> AWE
> >> >> CEn
> >> >> ARDY
> >> >> A2-Am Ai-Aj
> >> >> D0-Dk D0-Dk
> >> >>
> >> >> where n, m, and i,j,k are to be determined, the objective being to
> >> define
> >> >> signal equivalence and connectivity. There
> >> >> is no point to worry about number of pins without first carefully
> >> >> considering the underlying design.
> >> >>
> >> >> -Jeff
> >> >
> >> > --
> >> > Varun
> >>
> >>
> >
> >
> > --
> > Varun
>
--
Varun
First of all thanks for replying. I interspersed my replies with a * as
usual.*
On Wed, Aug 18, 2010 at 8:52 PM, Jeff Brower wrote:
> Varoonian-
>
> > Thank you. I just found out the PDT pins. They are actually muxed with
> the
> > EMIF A's EA 19 address pin once the PDT Control Register has been
> > appropriately set.
> >
> > Can you feed the FIFO status signals to the interrupt pins of the DSK ?
>
> Not sure. Since the DSP controls all SDRAM read/write (acting as "DMA
> engine", to use Xilinx terminology), and Xilinx
> doesn't show FIFO status signals (full, empty, etc) connected in any way,
> then I would assume that Xilinx expects the
> "other side" of the FIFO logic to always be slower (on average) than the
> SDRAM. For example, if initial SDRAM access
> is slow and the FIFO fills up a little, then subsequent (consecutive)
> accesses are fast and the FIFO will unwind.
>
> Could the FIFO completely fill up? Good question, depends a lot on your
> side of the FIFO. Suggest to ask Xilinx FAE
> about this.
>
> A question for your design: why do you need to know FIFO status? If
> you're writing DSP code to control DMA activity,
> then your code can receive a 'DMA done' interrupt to know when the DMA
> transfer is complete.
>
* IN my project an ADC at 200 MHz sends 8 bit differential LVDS to the
FIFO(FPGA) which is in turn read (32 bit ) by the DSP at the EMIF CLK
frequency (120 MHz) and stored in the SDRAM. So I am gonna do PDT.
Since I am doing DMA for the first time I am not very well versed in this
yet. If the FIFO becomes empty, the DSP needs to be intimated to stop the
READ.
*
>
> > What do you think about the interface between the DSK and FPGA ? I bought
> > the necessary connectors and cables. I think the only solution is to
> solder
> > them first before actually building a board.
>
> The cables should not solder to anything, they should crimp to connectors
> that match the board receptacles. Do you
> mean that since the connectors are not the same width, then you need an
> adapter card at one end? And this requires
> soldering? Otherwise I don't get you. What connectors and cables do you
> have? Maybe you can post a picture.
>
* regarding the cables. TI DSP have 0.05 inch pitch for their connectors
whereas Xilinx connectors have 0.1 inch pitch connectors.
These two do not mate, nor is any connector available. So for testing
purposes I cannot straight away build a board. Therefore I need to solder
cables from both connectors initially. If that works fine then I will build
a board.
*Thanks,
>
> -Jeff
>
> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower
> wrote:
> >
> >> Varoonian-
> >>
> >> > First of all, apologies for the really late reply as I fell sick.
> >> >
> >> > I have posted my replies with *.*
> >> >
> >> > A couple of initial questions / comments:
> >> >
> >> > 1) How long do you plan to make the cable between DSK6416 and Virtex-5
> >> EVM?
> >> > What type of cable are you using?
> >> >
> >> > *: Less than 4 inches. Since we are going to stack the DSP and FIFO
> >> one
> >> > above the other in order to reduce the cable length.*
> >> >
> >> > 2) Suggest to post to the group a two-column signal table, one column
> for
> >> > EMIF and other for V5 EVM, like this:
> >> >
> >> > * Since some glue logic is required I have pasted the image below
> that
> >> > describes the connectivity between the FPGA and the EMIF.*
> >> >
> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF are
> >> >
> >> > [image: fifo2emif.bmp]
> >> >
> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in the
> >> SDRAM
> >> > of the DSK 6416. This means that I need to perform a Peripheral Device
> >> > Transfer(PDT). Perform a PDT involves a different kind of interfacing.
> >> >
> >> > [image: PDT.JPG]
> >> >
> >> > *When I looked up the DSK 6416 datasheet, I can't look up for the PDT
> pin
> >> on
> >> > the EMIF A. Is the PDT pin an internal pin ??*
> >>
> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I don't
> >> know whether these pins are brought out to
> >> the DSK daughtercard connector -- you have to study the DSK board
> >> schematics. If not, then maybe you can find a PDT
> >> test point on the DSK board and run a wire to an unused pin on the
> >> daughtercard connector (or redefine an existing
> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the chip
> :-(
> >>
> >> -Jeff
> >>
> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower
> >> wrote:
> >> >
> >> >> Varun-
> >> >>
> >> >> > Does anyone know what is the interface used to connect the Virtex-5
> >> FPGA
> >> >> and
> >> >> > the the DSK6416 EMIF ?
> >> >> >
> >> >> > I know the connector to be used on the EMIF side is a Samtec TMS
> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
> >> >> Virtex-5.
> >> >> >
> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM
> aren't
> >> the
> >> >> > same.
> >> >>
> >> >> A couple of initial questions / comments:
> >> >>
> >> >> 1) How long do you plan to make the cable between DSK6416 and
> Virtex-5
> >> EVM?
> >> >> What type of cable are you using?
> >> >>
> >> >> 2) Suggest to post to the group a two-column signal table, one column
> >> for
> >> >> EMIF and other for V5 EVM, like this:
> >> >>
> >> >> DSK6461 EMIF Virtex-5 EVM
> >> >> ------------ ------------
> >> >> AWE
> >> >> CEn
> >> >> ARDY
> >> >> A2-Am Ai-Aj
> >> >> D0-Dk D0-Dk
> >> >>
> >> >> where n, m, and i,j,k are to be determined, the objective being to
> >> define
> >> >> signal equivalence and connectivity. There
> >> >> is no point to worry about number of pins without first carefully
> >> >> considering the underlying design.
> >> >>
> >> >> -Jeff
> >> >
> >> > --
> >> > Varun
> >>
> >>
> >
> >
> > --
> > Varun
>
--
Varun
Reply by ●August 20, 20102010-08-20
Varun-
>> For a continuous stream of incoming data the typical method is double
>> buffering (in your case, maybe split the FIFO in
>> half, or have 2 FIFOs). When each buffer is full the DSP is notified and
>> starts a DMA transfer, while input streaming
>> continues in the other buffer. The buffer transfers toggle back and forth.
>> To implement this, your FPGA would issue
>> some type of "buffer full" interrupt. If Xilinx hasn't defined a signal
>> for this then hopefully there is an unused
>> pin you can use.
>>
> * So two FIFO's connected back to back. The one near the DSP bursts out
> data when it is FULL.* Is that correct ?
No, side-by-side. Your FPGA logic writes A/D samples into FIFO A. When FIFO A is full, your logic:
-notifies the DSP
-switches to FIFO B and continues
writing A/D samples
The DSP then performs DMA transfers from FIFO A to SDRAM. Your logic would mux the DSP EMIF control signals so they
can be connected to either FIFO, as needed.
Also it's worth pointing out that you could use dual-port RAM in the FPGA also. A double-buffer scheme doesn't really
require FIFOs, plus the DSP can DMA transfer a buffer to SDRAM faster than your A/D 32-bit wide samples can fill one
(at least we assume that, otherwise your project can never work).
> *The FIFO does have a FIFO full
> signal and empty signal. Can you suggest any literature on this ?
First I would think it's straightforward to connect various FIFO signals to pins that go to the expansion connector on
the Virtex5 EVM. Have you tried this yet?
Second, are you asking Xilinx these questions? I don't see your posts on comp.arch.fpga or Xilinx 'programmable
logic' forums. You are using an Xilinx app note as the key basis for your design, so if you run into doubts then you
should ask Xilinx guys.
-Jeff
> My guess is a hand-soldered 4" cable is going to be problematic for your
>> project -- 120 MHz clock and data transfers
>> are probably going to get smushed. You might look into Mictor type of
>> cables (individually shielded conductors);
>> these are used for logic analyzers. Another idea would be to use
>> LVDS-supported pins on the Virtex5 EVM board and
>> make (or purchase) a daughtercard for the DSK board that has LVDS
>> transceivers and an appropriate connector. I
>> suggest that you do some serious digging on this, and ask for advice both
>> on Xilinx forum and TI e2e forum.
>> * I agree. Xilinx FPGA does have pins which support LVDS. I * checked out
> *MICTOR ( ones mfg by signalogic too. ) I am very skeptical whether I would
> be able to get* MICTORs that could mate with the Xilinx 0.05 inch headers. I
> will have a look. Thanks a lot for your inputs Mr.Bower.
>
> Thanks,
>
>>
>> -Jeff
>>
>> >> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower
>> >> wrote:
>> >> >
>> >> >> Varoonian-
>> >> >>
>> >> >> > First of all, apologies for the really late reply as I fell sick.
>> >> >> >
>> >> >> > I have posted my replies with *.*
>> >> >> >
>> >> >> > A couple of initial questions / comments:
>> >> >> >
>> >> >> > 1) How long do you plan to make the cable between DSK6416 and
>> Virtex-5
>> >> >> EVM?
>> >> >> > What type of cable are you using?
>> >> >> >
>> >> >> > *: Less than 4 inches. Since we are going to stack the DSP and
>> FIFO
>> >> >> one
>> >> >> > above the other in order to reduce the cable length.*
>> >> >> >
>> >> >> > 2) Suggest to post to the group a two-column signal table, one
>> column
>> >> for
>> >> >> > EMIF and other for V5 EVM, like this:
>> >> >> >
>> >> >> > * Since some glue logic is required I have pasted the image
>> below
>> >> that
>> >> >> > describes the connectivity between the FPGA and the EMIF.*
>> >> >> >
>> >> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF
>> are
>> >> >> >
>> >> >> > [image: fifo2emif.bmp]
>> >> >> >
>> >> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in
>> the
>> >> >> SDRAM
>> >> >> > of the DSK 6416. This means that I need to perform a Peripheral
>> Device
>> >> >> > Transfer(PDT). Perform a PDT involves a different kind of
>> interfacing.
>> >> >> >
>> >> >> > [image: PDT.JPG]
>> >> >> >
>> >> >> > *When I looked up the DSK 6416 datasheet, I can't look up for the
>> PDT
>> >> pin
>> >> >> on
>> >> >> > the EMIF A. Is the PDT pin an internal pin ??*
>> >> >>
>> >> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I
>> don't
>> >> >> know whether these pins are brought out to
>> >> >> the DSK daughtercard connector -- you have to study the DSK board
>> >> >> schematics. If not, then maybe you can find a PDT
>> >> >> test point on the DSK board and run a wire to an unused pin on the
>> >> >> daughtercard connector (or redefine an existing
>> >> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the
>> chip
>> >> :-(
>> >> >>
>> >> >> -Jeff
>> >> >>
>> >> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower <
>> j...@signalogic.com>
>> >> >> wrote:
>> >> >> >
>> >> >> >> Varun-
>> >> >> >>
>> >> >> >> > Does anyone know what is the interface used to connect the
>> Virtex-5
>> >> >> FPGA
>> >> >> >> and
>> >> >> >> > the the DSK6416 EMIF ?
>> >> >> >> >
>> >> >> >> > I know the connector to be used on the EMIF side is a Samtec TMS
>> >> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
>> >> >> >> Virtex-5.
>> >> >> >> >
>> >> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM
>> >> aren't
>> >> >> the
>> >> >> >> > same.
>> >> >> >>
>> >> >> >> A couple of initial questions / comments:
>> >> >> >>
>> >> >> >> 1) How long do you plan to make the cable between DSK6416 and
>> >> Virtex-5
>> >> >> EVM?
>> >> >> >> What type of cable are you using?
>> >> >> >>
>> >> >> >> 2) Suggest to post to the group a two-column signal table, one
>> column
>> >> >> for
>> >> >> >> EMIF and other for V5 EVM, like this:
>> >> >> >>
>> >> >> >> DSK6461 EMIF Virtex-5 EVM
>> >> >> >> ------------ ------------
>> >> >> >> AWE
>> >> >> >> CEn
>> >> >> >> ARDY
>> >> >> >> A2-Am Ai-Aj
>> >> >> >> D0-Dk D0-Dk
>> >> >> >>
>> >> >> >> where n, m, and i,j,k are to be determined, the objective being to
>> >> >> define
>> >> >> >> signal equivalence and connectivity. There
>> >> >> >> is no point to worry about number of pins without first carefully
>> >> >> >> considering the underlying design.
>> >> >> >>
>> >> >> >> -Jeff
> --
> Varun
>
_____________________________________
>> For a continuous stream of incoming data the typical method is double
>> buffering (in your case, maybe split the FIFO in
>> half, or have 2 FIFOs). When each buffer is full the DSP is notified and
>> starts a DMA transfer, while input streaming
>> continues in the other buffer. The buffer transfers toggle back and forth.
>> To implement this, your FPGA would issue
>> some type of "buffer full" interrupt. If Xilinx hasn't defined a signal
>> for this then hopefully there is an unused
>> pin you can use.
>>
> * So two FIFO's connected back to back. The one near the DSP bursts out
> data when it is FULL.* Is that correct ?
No, side-by-side. Your FPGA logic writes A/D samples into FIFO A. When FIFO A is full, your logic:
-notifies the DSP
-switches to FIFO B and continues
writing A/D samples
The DSP then performs DMA transfers from FIFO A to SDRAM. Your logic would mux the DSP EMIF control signals so they
can be connected to either FIFO, as needed.
Also it's worth pointing out that you could use dual-port RAM in the FPGA also. A double-buffer scheme doesn't really
require FIFOs, plus the DSP can DMA transfer a buffer to SDRAM faster than your A/D 32-bit wide samples can fill one
(at least we assume that, otherwise your project can never work).
> *The FIFO does have a FIFO full
> signal and empty signal. Can you suggest any literature on this ?
First I would think it's straightforward to connect various FIFO signals to pins that go to the expansion connector on
the Virtex5 EVM. Have you tried this yet?
Second, are you asking Xilinx these questions? I don't see your posts on comp.arch.fpga or Xilinx 'programmable
logic' forums. You are using an Xilinx app note as the key basis for your design, so if you run into doubts then you
should ask Xilinx guys.
-Jeff
> My guess is a hand-soldered 4" cable is going to be problematic for your
>> project -- 120 MHz clock and data transfers
>> are probably going to get smushed. You might look into Mictor type of
>> cables (individually shielded conductors);
>> these are used for logic analyzers. Another idea would be to use
>> LVDS-supported pins on the Virtex5 EVM board and
>> make (or purchase) a daughtercard for the DSK board that has LVDS
>> transceivers and an appropriate connector. I
>> suggest that you do some serious digging on this, and ask for advice both
>> on Xilinx forum and TI e2e forum.
>> * I agree. Xilinx FPGA does have pins which support LVDS. I * checked out
> *MICTOR ( ones mfg by signalogic too. ) I am very skeptical whether I would
> be able to get* MICTORs that could mate with the Xilinx 0.05 inch headers. I
> will have a look. Thanks a lot for your inputs Mr.Bower.
>
> Thanks,
>
>>
>> -Jeff
>>
>> >> > On Wed, Aug 18, 2010 at 1:54 PM, Jeff Brower
>> >> wrote:
>> >> >
>> >> >> Varoonian-
>> >> >>
>> >> >> > First of all, apologies for the really late reply as I fell sick.
>> >> >> >
>> >> >> > I have posted my replies with *.*
>> >> >> >
>> >> >> > A couple of initial questions / comments:
>> >> >> >
>> >> >> > 1) How long do you plan to make the cable between DSK6416 and
>> Virtex-5
>> >> >> EVM?
>> >> >> > What type of cable are you using?
>> >> >> >
>> >> >> > *: Less than 4 inches. Since we are going to stack the DSP and
>> FIFO
>> >> >> one
>> >> >> > above the other in order to reduce the cable length.*
>> >> >> >
>> >> >> > 2) Suggest to post to the group a two-column signal table, one
>> column
>> >> for
>> >> >> > EMIF and other for V5 EVM, like this:
>> >> >> >
>> >> >> > * Since some glue logic is required I have pasted the image
>> below
>> >> that
>> >> >> > describes the connectivity between the FPGA and the EMIF.*
>> >> >> >
>> >> >> > As per XAPP753 , the connections between the FIFO(FPGA) and EMIF
>> are
>> >> >> >
>> >> >> > [image: fifo2emif.bmp]
>> >> >> >
>> >> >> > But, I only want to read the FIFO(Virtex-5 FPGA) and store it in
>> the
>> >> >> SDRAM
>> >> >> > of the DSK 6416. This means that I need to perform a Peripheral
>> Device
>> >> >> > Transfer(PDT). Perform a PDT involves a different kind of
>> interfacing.
>> >> >> >
>> >> >> > [image: PDT.JPG]
>> >> >> >
>> >> >> > *When I looked up the DSK 6416 datasheet, I can't look up for the
>> PDT
>> >> pin
>> >> >> on
>> >> >> > the EMIF A. Is the PDT pin an internal pin ??*
>> >> >>
>> >> >> /APDT and /BPDT are C641x EMIF pins (see the C6416 data sheet). I
>> don't
>> >> >> know whether these pins are brought out to
>> >> >> the DSK daughtercard connector -- you have to study the DSK board
>> >> >> schematics. If not, then maybe you can find a PDT
>> >> >> test point on the DSK board and run a wire to an unused pin on the
>> >> >> daughtercard connector (or redefine an existing
>> >> >> pin). Hopefully the PDT pin is not "NC" and thus buried under the
>> chip
>> >> :-(
>> >> >>
>> >> >> -Jeff
>> >> >>
>> >> >> > On Thu, Jul 22, 2010 at 1:50 PM, Jeff Brower <
>> j...@signalogic.com>
>> >> >> wrote:
>> >> >> >
>> >> >> >> Varun-
>> >> >> >>
>> >> >> >> > Does anyone know what is the interface used to connect the
>> Virtex-5
>> >> >> FPGA
>> >> >> >> and
>> >> >> >> > the the DSK6416 EMIF ?
>> >> >> >> >
>> >> >> >> > I know the connector to be used on the EMIF side is a Samtec TMS
>> >> >> >> > 140-32-S-D-LC but I have no idea about interfacing that with the
>> >> >> >> Virtex-5.
>> >> >> >> >
>> >> >> >> > The no. of pins on the EMIF side and the the FPGA Virtex 5 EVM
>> >> aren't
>> >> >> the
>> >> >> >> > same.
>> >> >> >>
>> >> >> >> A couple of initial questions / comments:
>> >> >> >>
>> >> >> >> 1) How long do you plan to make the cable between DSK6416 and
>> >> Virtex-5
>> >> >> EVM?
>> >> >> >> What type of cable are you using?
>> >> >> >>
>> >> >> >> 2) Suggest to post to the group a two-column signal table, one
>> column
>> >> >> for
>> >> >> >> EMIF and other for V5 EVM, like this:
>> >> >> >>
>> >> >> >> DSK6461 EMIF Virtex-5 EVM
>> >> >> >> ------------ ------------
>> >> >> >> AWE
>> >> >> >> CEn
>> >> >> >> ARDY
>> >> >> >> A2-Am Ai-Aj
>> >> >> >> D0-Dk D0-Dk
>> >> >> >>
>> >> >> >> where n, m, and i,j,k are to be determined, the objective being to
>> >> >> define
>> >> >> >> signal equivalence and connectivity. There
>> >> >> >> is no point to worry about number of pins without first carefully
>> >> >> >> considering the underlying design.
>> >> >> >>
>> >> >> >> -Jeff
> --
> Varun
>
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