Hi,
I am working on the C6748 DSP to develop a simple denoising application using an
FIR filter with 147 taps. I am using the DSP BIOS as well. The board is an OMAP
L138 by PD LOGIC having a crystal of 24MHz. The idea is to read in 2 channel
audio from the audio input port (a noisy sound from the computer) and filter the
data from the channels separately and put them together again before sending it
out the audio output port. The sound is sampled at 8KHz and is read through an
interrupt. The software set-up is as following:
1. A PRD (every 1s) is used to read switches based on their combination, a
different set of filter coefficients is loaded using probepoints.
2. When an interrupt occurs, in the ISR the data is read, the data from each
channel is separated and the filtering algorithm (a simple FIR implementation
with a circular buffer) is applied to each of the two channels separately. It is
then combined and put out the audio part. This is actually what is supposed to
happen.
The problem I am facing is that with out loading any thing through the
probepoints, I am only able to perform 32 floating point multiplications in
every interrupt. I am confused on whether this should be a problem or not?
As far as I understand, the clock cycle should be 4*24Mhz (because of the PLL)
leaving one clock cycle to be 10.4166ns. Since the sound is sampled at 8KHz that
leaves me 125 microseconds to do all the software part (including my code, PRD
and other things).
Thank you very much.
_____________________________________
C6748 clock cycle speed
Started by ●January 17, 2013
Reply by ●March 2, 20132013-03-02
Are you processing a single sample at every interrupt?
Jose
Hi,
>
>I am working on the C6748 DSP to develop a simple denoising application using an FIR filter with 147 taps. I am using the DSP BIOS as well. The board is an OMAP L138 by PD LOGIC having a crystal of 24MHz. The idea is to read in 2 channel audio from the audio input port (a noisy sound from the computer) and filter the data from the channels separately and put them together again before sending it out the audio output port. The sound is sampled at 8KHz and is read through an interrupt. The software set-up is as following:
>
>1. A PRD (every 1s) is used to read switches based on their combination, a different set of filter coefficients is loaded using probepoints.
>
>2. When an interrupt occurs, in the ISR the data is read, the data from each channel is separated and the filtering algorithm (a simple FIR implementation with a circular buffer) is applied to each of the two channels separately. It is then combined and put out the audio part. This is actually what is supposed to happen.
>
>The problem I am facing is that with out loading any thing through the probepoints, I am only able to perform 32 floating point multiplications in every interrupt. I am confused on whether this should be a problem or not?
>
>As far as I understand, the clock cycle should be 4*24Mhz (because of the PLL) leaving one clock cycle to be 10.4166ns. Since the sound is sampled at 8KHz that leaves me 125 microseconds to do all the software part (including my code, PRD and other things).
>
>Thank you very much.
>
>_____________________________________
_____________________________________
Jose
Hi,
>
>I am working on the C6748 DSP to develop a simple denoising application using an FIR filter with 147 taps. I am using the DSP BIOS as well. The board is an OMAP L138 by PD LOGIC having a crystal of 24MHz. The idea is to read in 2 channel audio from the audio input port (a noisy sound from the computer) and filter the data from the channels separately and put them together again before sending it out the audio output port. The sound is sampled at 8KHz and is read through an interrupt. The software set-up is as following:
>
>1. A PRD (every 1s) is used to read switches based on their combination, a different set of filter coefficients is loaded using probepoints.
>
>2. When an interrupt occurs, in the ISR the data is read, the data from each channel is separated and the filtering algorithm (a simple FIR implementation with a circular buffer) is applied to each of the two channels separately. It is then combined and put out the audio part. This is actually what is supposed to happen.
>
>The problem I am facing is that with out loading any thing through the probepoints, I am only able to perform 32 floating point multiplications in every interrupt. I am confused on whether this should be a problem or not?
>
>As far as I understand, the clock cycle should be 4*24Mhz (because of the PLL) leaving one clock cycle to be 10.4166ns. Since the sound is sampled at 8KHz that leaves me 125 microseconds to do all the software part (including my code, PRD and other things).
>
>Thank you very much.
>
>_____________________________________
_____________________________________
Reply by ●March 2, 20132013-03-02
Jose,
From your post, I think you are doing this the hard way. I.E. processing one
sample at each interrupt.
A much better method:
Use the EDMA to perform all the input/output processing
set the EDMA to produce a EOL interrupt when the current array is full
in the EOL interrupt::
set the EDMA to read into the second input array
set the EDMA to write from the second output array
start a software interrupt to process from the first input array to the first
output array
exit the EOL interrupt
Start the EDMA running...
In the software interrupt, there is now, not the time to process a single input
sample, but rather the time needed to fill the input buffer (some power of 2
input samples.)
It helps, when debugging, to keep some tracking info to assure the software
interrupt is completing quickly enough.
Don't use print statements or anything like that as they will take too long.
The T.I. web site documents contain several examples of exactly how to implement
the EDMA/double buffering of input and output/EOL interrupt processing.
R. Williams
Select one of the output arrays to initially output
use the EDMA to input the samples into a input 'row/array/buffer'
have the EDMA trigger a interrupt when the input 'row/array/buffer' is full
The interrupt does these things:
--switches the EDMA to an alternate input 'row/array/buffer'
--triggers a software interrupt to perform the actual processing, on the
original 'row/array/buffer'
--switches the EDMA
---------- Original Message -----------
From: j...@yahoo.com.ar
To: c...
Sent: Sat, 02 Mar 2013 12:43:20 -0500
Subject: [c6x] Re: C6748 clock cycle speed
> Are you processing a single sample at every interrupt?
>
> Jose
>
> Hi,
> >
> >I am working on the C6748 DSP to develop a simple denoising application using
an FIR filter with 147 taps. I am using the DSP BIOS as well. The board is an
OMAP L138 by PD LOGIC having a crystal of 24MHz. The idea is to read in 2
channel audio from the audio input port (a noisy sound from the computer) and
filter the data from the channels separately and put them together again before
sending it out the audio output port. The sound is sampled at 8KHz and is read
through an interrupt. The software set-up is as following:
> >
> >1. A PRD (every 1s) is used to read switches based on their combination, a
different set of filter coefficients is loaded using probepoints.
> >
> >2. When an interrupt occurs, in the ISR the data is read, the data from each
channel is separated and the filtering algorithm (a simple FIR implementation
with a circular buffer) is applied to each of the two channels separately. It is
then combined and put out the audio part. This is actually what is supposed to
happen.
> >
> >The problem I am facing is that with out loading any thing through the
probepoints, I am only able to perform 32 floating point multiplications in
every interrupt. I am confused on whether this should be a problem or not?
> >
> >As far as I understand, the clock cycle should be 4*24Mhz (because of the
PLL) leaving one clock cycle to be 10.4166ns. Since the sound is sampled at 8KHz
that leaves me 125 microseconds to do all the software part (including my code,
PRD and other things).
> >
> >Thank you very much.
> >
> >_____________________________________
> >
> >
------- End of Original Message -------
_____________________________________
From your post, I think you are doing this the hard way. I.E. processing one
sample at each interrupt.
A much better method:
Use the EDMA to perform all the input/output processing
set the EDMA to produce a EOL interrupt when the current array is full
in the EOL interrupt::
set the EDMA to read into the second input array
set the EDMA to write from the second output array
start a software interrupt to process from the first input array to the first
output array
exit the EOL interrupt
Start the EDMA running...
In the software interrupt, there is now, not the time to process a single input
sample, but rather the time needed to fill the input buffer (some power of 2
input samples.)
It helps, when debugging, to keep some tracking info to assure the software
interrupt is completing quickly enough.
Don't use print statements or anything like that as they will take too long.
The T.I. web site documents contain several examples of exactly how to implement
the EDMA/double buffering of input and output/EOL interrupt processing.
R. Williams
Select one of the output arrays to initially output
use the EDMA to input the samples into a input 'row/array/buffer'
have the EDMA trigger a interrupt when the input 'row/array/buffer' is full
The interrupt does these things:
--switches the EDMA to an alternate input 'row/array/buffer'
--triggers a software interrupt to perform the actual processing, on the
original 'row/array/buffer'
--switches the EDMA
---------- Original Message -----------
From: j...@yahoo.com.ar
To: c...
Sent: Sat, 02 Mar 2013 12:43:20 -0500
Subject: [c6x] Re: C6748 clock cycle speed
> Are you processing a single sample at every interrupt?
>
> Jose
>
> Hi,
> >
> >I am working on the C6748 DSP to develop a simple denoising application using
an FIR filter with 147 taps. I am using the DSP BIOS as well. The board is an
OMAP L138 by PD LOGIC having a crystal of 24MHz. The idea is to read in 2
channel audio from the audio input port (a noisy sound from the computer) and
filter the data from the channels separately and put them together again before
sending it out the audio output port. The sound is sampled at 8KHz and is read
through an interrupt. The software set-up is as following:
> >
> >1. A PRD (every 1s) is used to read switches based on their combination, a
different set of filter coefficients is loaded using probepoints.
> >
> >2. When an interrupt occurs, in the ISR the data is read, the data from each
channel is separated and the filtering algorithm (a simple FIR implementation
with a circular buffer) is applied to each of the two channels separately. It is
then combined and put out the audio part. This is actually what is supposed to
happen.
> >
> >The problem I am facing is that with out loading any thing through the
probepoints, I am only able to perform 32 floating point multiplications in
every interrupt. I am confused on whether this should be a problem or not?
> >
> >As far as I understand, the clock cycle should be 4*24Mhz (because of the
PLL) leaving one clock cycle to be 10.4166ns. Since the sound is sampled at 8KHz
that leaves me 125 microseconds to do all the software part (including my code,
PRD and other things).
> >
> >Thank you very much.
> >
> >_____________________________________
> >
> >
------- End of Original Message -------
_____________________________________
