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I'm working on upgrading a C67xx board. Currently we are using Micron SDRAMs, same as the C67xx DSKs. Question: is there a good reason to run the additional address lines (EA16-EA21) or other signals to NC pins on the SDRAMs? I can't find any other device types such as SRAM or Flash that are pin-compatible with the Microns. Also, I can't find other SDRAMs that are 100% are pin-compatible, although something like Fujitsu is close and might work if the NCs are GND or pulled up. Micron's package is an 86-pin TSOP; is there a JEDEC standard that defines the NCs for this package? Thanks. -Jeff |
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SDRAM pin-compatibility question
Started by ●September 22, 2003
Reply by ●September 22, 20032003-09-22
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Jane- > Check this out. > http://download.micron.com/pdf/technotes/TN4808.pdf > If this helps, you might regret that you didn't search hard enough the internet for > an answer. ;-) Hmmm, you haven't posted in a while. Seems a very smart person was lurking :-) Thanks for the PDF link, this helps for other Micron, but not for other devices or other manufacturers. The NC pins in question are 14, 30, 57, 69, 70, and 73. For example, Fujitsu uses those for data strobes, an alternative negative-edge clock, and a Vref pin. I did notice this in the PDF: "A12 pin location has not been set by JEDEC on the TSOP package". This note was in reference to a 512 Mb part, or 16M x 32, but I don't see that Micron has preliminary info for that yet on their web site. So A12 is at least one line I can try to figure out and run. -Jeff > -----Original Message----- > From: Jeff Brower [mailto:] > Sent: Monday, September 22, 2003 8:51 AM > To: > Subject: [c6x] SDRAM pin-compatibility question > > I'm working on upgrading a C67xx board. Currently we are using Micron SDRAMs, same > > as the C67xx DSKs. > > Question: is there a good reason to run the additional address lines (EA16-EA21) > or > other signals to NC pins on the SDRAMs? I can't find any other device types such > as > SRAM or Flash that are pin-compatible with the Microns. Also, I can't find other > SDRAMs that are 100% are pin-compatible, although something like Fujitsu is close > and > might work if the NCs are GND or pulled up. Micron's package is an 86-pin TSOP; is > > there a JEDEC standard that defines the NCs for this package? > > Thanks. > > -Jeff |
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Reply by ●September 22, 20032003-09-22
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Check this out.
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Reply by ●September 22, 20032003-09-22
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At 12:27 PM 9/22/2003, Jeff Brower wrote: >Jane- > > > Check this out. > > http://download.micron.com/pdf/technotes/TN4808.pdf > > If this helps, you might regret that you didn't search hard enough the > internet for > > an answer. ;-) > >Hmmm, you haven't posted in a while. Seems a very smart person was >lurking :-) > >Thanks for the PDF link, this helps for other Micron, but not for other >devices or >other manufacturers. The NC pins in question are 14, 30, 57, 69, 70, and >73. For >example, Fujitsu uses those for data strobes, an alternative negative-edge >clock, and >a Vref pin. > >I did notice this in the PDF: "A12 pin location has not been set by JEDEC >on the >TSOP package". This note was in reference to a 512 Mb part, or 16M x 32, >but I don't >see that Micron has preliminary info for that yet on their web site. So >A12 is at >least one line I can try to figure out and run. It has been awhile since I looked at this problem, but I seem to recall that the C67 makes life difficult for you when trying to provide for multiple SDRAM sizes. When I looked at this awhile back, I found that the best I could do is to lay out the PCB for two SDRAM sizes and that required placing two footprints (overlapping) on the PCB. Take a close look at the TI EMIF data and I think you will find that they goof up the pinout between different SDRAM sizes. You need to map the address pins differently, not just provide more or less of them. When I posted about this either here or in the newsgroups, someone suggested that I could get two sizes by using two SDRAM footprints slightly offset. Like this... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Each footprint is wired for a separate size part. By overlapping them, I don't need to waste space for complete second footprint. The 86 pin part is a 32 bit wide data part, right? Are you getting decent pricing on this? I decided to go with a pair of x16 parts because the x32s seem to be more proprietary (and I just barely had the room). Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX |
Reply by ●September 22, 20032003-09-22
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Rick- > It has been awhile since I looked at this problem, but I seem to recall > that the C67 makes life difficult for you when trying to provide for > multiple SDRAM sizes. When I looked at this awhile back, I found that the > best I could do is to lay out the PCB for two SDRAM sizes and that required > placing two footprints (overlapping) on the PCB. Take a close look at the > TI EMIF data and I think you will find that they goof up the pinout between > different SDRAM sizes. You need to map the address pins differently, not > just provide more or less of them. Do you remember if the error occurs at EA16? That's the next line. > When I posted about this either here or in the newsgroups, someone > suggested that I could get two sizes by using two SDRAM footprints slightly > offset. Like this... > > 0 0 0 0 0 0 0 0 0 0 0 > 0 0 0 0 0 0 0 0 0 0 0 > > 0 0 0 0 0 0 0 0 0 0 0 > 0 0 0 0 0 0 0 0 0 0 0 > > Each footprint is wired for a separate size part. By overlapping them, I > don't need to waste space for complete second footprint. Right, which I think I've seen on the DSK boards. But in the case of a 512 Mb (16M x 32) device, there will be one more addr line (according to Micron's site). My hope is that one site should handle 2, 4, and 8M (currently available) and 16M in the future. But I'm having a hard time to figure out which pin is A12. A search of JEDEC's website and various SDRAM mfg sites indicates that even 3 yrs later, it still has not been assigned for the 86-pin TSOP package. > The 86 pin part is a 32 bit wide data part, right? Yes. > Are you getting decent pricing on this? Not as good as two x16s. > I decided to go with a pair of x16 parts because the x32s > seem to be more proprietary (and I just barely had the room). We are very space-sensitive. Even when more expensive, we would still use just one x32 device -Jeff |
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Reply by ●September 22, 20032003-09-22
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> The 86 pin part is a 32 bit wide data part, right? Are you getting
decent > pricing on this? I decided to go with a pair of x16 parts because the x32s > seem to be more proprietary (and I just barely had the room). we are using 2Mx32 parts with the C6711 and C6713. We use the Micron, Samsung and ISSI versions interchangeably and have had no problems so far (143MHz speed grade). They cost us around $3.00 earlier this year - I believe the cost has gone up slightly since then. -steve ------------------------ Stephen Turner AudioScience, Inc. www.audioscience.com ----- Original Message ----- From: "Arius - Rick Collins" <> To: "Jeff Brower" <>; <> Sent: Monday, September 22, 2003 1:47 PM Subject: Re: [c6x] SDRAM pin-compatibility question > At 12:27 PM 9/22/2003, Jeff Brower wrote: > >Jane- > > > > > Check this out. > > > http://download.micron.com/pdf/technotes/TN4808.pdf > > > If this helps, you might regret that you didn't search hard enough the > > internet for > > > an answer. ;-) > > > >Hmmm, you haven't posted in a while. Seems a very smart person was > >lurking :-) > > > >Thanks for the PDF link, this helps for other Micron, but not for other > >devices or > >other manufacturers. The NC pins in question are 14, 30, 57, 69, 70, and > >73. For > >example, Fujitsu uses those for data strobes, an alternative negative-edge > >clock, and > >a Vref pin. > > > >I did notice this in the PDF: "A12 pin location has not been set by JEDEC > >on the > >TSOP package". This note was in reference to a 512 Mb part, or 16M x 32, > >but I don't > >see that Micron has preliminary info for that yet on their web site. So > >A12 is at > >least one line I can try to figure out and run. > > It has been awhile since I looked at this problem, but I seem to recall > that the C67 makes life difficult for you when trying to provide for > multiple SDRAM sizes. When I looked at this awhile back, I found that the > best I could do is to lay out the PCB for two SDRAM sizes and that required > placing two footprints (overlapping) on the PCB. Take a close look at the > TI EMIF data and I think you will find that they goof up the pinout between > different SDRAM sizes. You need to map the address pins differently, not > just provide more or less of them. > > When I posted about this either here or in the newsgroups, someone > suggested that I could get two sizes by using two SDRAM footprints slightly > offset. Like this... > 0 0 0 0 0 0 0 0 0 0 0 > 0 0 0 0 0 0 0 0 0 0 0 > 0 0 0 0 0 0 0 0 0 0 0 > 0 0 0 0 0 0 0 0 0 0 0 > > Each footprint is wired for a separate size part. By overlapping them, I > don't need to waste space for complete second footprint. > > The 86 pin part is a 32 bit wide data part, right? Are you getting decent > pricing on this? I decided to go with a pair of x16 parts because the x32s > seem to be more proprietary (and I just barely had the room). > > Rick Collins > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX > _____________________________________ > Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. > > _____________________________________ > About this discussion group: > > To Join: Send an email to > > To Post: Send an email to > > To Leave: Send an email to > > Archives: http://www.yahoogroups.com/group/c6x > > Other Groups: http://www.dsprelated.com > ">http://docs.yahoo.com/info/terms/ |
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Reply by ●September 22, 20032003-09-22
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At 05:02 PM 9/22/2003, you wrote: >Rick- > > > It has been awhile since I looked at this problem, but I seem to recall > > that the C67 makes life difficult for you when trying to provide for > > multiple SDRAM sizes. When I looked at this awhile back, I found that the > > best I could do is to lay out the PCB for two SDRAM sizes and that required > > placing two footprints (overlapping) on the PCB. Take a close look at the > > TI EMIF data and I think you will find that they goof up the pinout between > > different SDRAM sizes. You need to map the address pins differently, not > > just provide more or less of them. > >Do you remember if the error occurs at EA16? That's the next line. You need to read the C67 documentation. IIRC, it is not one pin that is off, it is the whole of the address bus that gets moved by one pin on the C67 between sizes. They did a crappy job on their internal muxing between sizes. > > When I posted about this either here or in the newsgroups, someone > > suggested that I could get two sizes by using two SDRAM footprints slightly > > offset. Like this... > > > > 0 0 0 0 0 0 0 0 0 0 0 > > 0 0 0 0 0 0 0 0 0 0 0 > > > > 0 0 0 0 0 0 0 0 0 0 0 > > 0 0 0 0 0 0 0 0 0 0 0 > > > > Each footprint is wired for a separate size part. By overlapping them, I > > don't need to waste space for complete second footprint. > >Right, which I think I've seen on the DSK boards. But in the case of a >512 Mb (16M x >32) device, there will be one more addr line (according to Micron's >site). My hope >is that one site should handle 2, 4, and 8M (currently available) and 16M >in the >future. I think you will need a different footprint for each size. I also think the C6711 will not handle sizes above some max, which may be 256K, but I'm not sure. >But I'm having a hard time to figure out which pin is A12. A search of >JEDEC's >website and various SDRAM mfg sites indicates that even 3 yrs later, it >still has not >been assigned for the 86-pin TSOP package. The bottom line is pick your vendors and see how they do it. I seem to recall Toshiba as being a potential second source for Micron. You may find more than one "standard", but I doubt that each vendor will be unique. They know that many companies require a second source. > > The 86 pin part is a 32 bit wide data part, right? > >Yes. > > > Are you getting decent pricing on this? > >Not as good as two x16s. > > > I decided to go with a pair of x16 parts because the x32s > > seem to be more proprietary (and I just barely had the room). > >We are very space-sensitive. Even when more expensive, we would still use >just one >x32 device You might also look at the newer tiny sTSSOP parts (Samsung among others). They were new about a year or more ago and should be in production by now. I think they are targeted to the laptop memory module market and are about half the size of a standard 56 pin TSSOP. Since they are for commodity memory, they should not be overly expensive. If you find anything out about these, let me know. If they are commonly available, I would like to take a second look at them. I believe there are also BGA parts (Micron, et al). Maybe I will do a little digging myself... Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX |
Reply by ●September 22, 20032003-09-22
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At 05:38 PM 9/22/2003, Stephen Turner wrote: > > The 86 pin part is a 32 bit wide data part, right? Are you getting decent > > pricing on this? I decided to go with a pair of x16 parts because the >x32s > > seem to be more proprietary (and I just barely had the room). > >we are using 2Mx32 parts with the C6711 and C6713. We use the Micron, >Samsung and ISSI versions interchangeably and have had no problems so far >(143MHz speed grade). They cost us around $3.00 earlier this year - I >believe the cost has gone up slightly since then. What part number and what package are you using? I have not visited SDRAMs in about a year and I should probably take a second look. Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX |
Reply by ●September 22, 20032003-09-22
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Rick We're using: Micron MT48LC2M32B2TG-7 Samsung K4S643232E-TC70 ISSI IS42S32200A-7T -steve ------------------------ Stephen Turner AudioScience, Inc. www.audioscience.com ----- Original Message ----- From: "Arius - Rick Collins" <> To: "Stephen Turner" <>; <> Sent: Monday, September 22, 2003 3:06 PM Subject: Re: [c6x] SDRAM pin-compatibility question > At 05:38 PM 9/22/2003, Stephen Turner wrote: > > > The 86 pin part is a 32 bit wide data part, right? Are you getting decent > > > pricing on this? I decided to go with a pair of x16 parts because the > >x32s > > > seem to be more proprietary (and I just barely had the room). > > > >we are using 2Mx32 parts with the C6711 and C6713. We use the Micron, > >Samsung and ISSI versions interchangeably and have had no problems so far > >(143MHz speed grade). They cost us around $3.00 earlier this year - I > >believe the cost has gone up slightly since then. > > What part number and what package are you using? I have not visited SDRAMs > in about a year and I should probably take a second look. > > Rick Collins > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX > |
Reply by ●September 23, 20032003-09-23
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Rick- > You need to read the C67 documentation. IIRC, it is not one pin that is > off, it is the whole of the address bus that gets moved by one pin on the > C67 between sizes... Ok. > I think you will need a different footprint for each size. I also think > the C6711 will not handle sizes above some max, which may be 256K, but I'm > not sure. We've tried 2, 4, and 8M x 32, and those are Ok in the same footprint. Note that difference between 4 and 8 is an extra column address line, so no extra EMIF lines need to be run from the C6xxx. > The bottom line is pick your vendors and see how they do it. I seem to > recall Toshiba as being a potential second source for Micron. You may find > more than one "standard", but I doubt that each vendor will be > unique. They know that many companies require a second source. Thanks, I will recheck Toshiba. > You might also look at the newer tiny sTSSOP parts (Samsung among > others). They were new about a year or more ago and should be in > production by now. I think they are targeted to the laptop memory module > market and are about half the size of a standard 56 pin TSSOP. Since they > are for commodity memory, they should not be overly expensive. If you find > anything out about these, let me know. If they are commonly available, I > would like to take a second look at them. I believe there are also BGA > parts (Micron, et al). Samsung seems to not have any x32 organization. Yes the BGAs are an option, and Micron has those. But they are definitely expensive and have a long lead-time. We are using BGA versions for some high channel density VoIP PTMC boards where their extra margin gets buried in the higher cost of those boards. -Jeff |
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