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Problems with C6711DSK and EDMA transfer

Started by Juan Torres ●May 27, 2004
Hi c6x Group,

I am working with the C6711 DSK (150 MHz clock) and a
THS1206 Daughter Board, which has 4 channels and a
maximum sampling frequency of 6 MSPS for the 4
channels. I was able to produce a code to acquire data
from this ADC for 4 channels with sampling frequency
of 25 kHz per channel using pingpong buffering scheme
and EDMA transfer. The problem that I am having is
that the first values of every buffer processed are
not the values of the signal. Ironically, these values
have the same form of the signal but the are bigger by
a factor of 2 or a multiple of 2 (as if a bit has been
added to the right side of the value).

For example, in this e-mail, I am showing 3 graphs.
One of the graphs shows a signal which represents the
result of adding the 4 channels, which are receiving a
purely sinosioidal signal with the same phase. A
second graph shows a zoom of the signal. The width of
each ping/pong buffer is 12000 shorts (3000 per
channel). Since the output value is the sum of the 4
channels, the output buffer shows the result of a
ping/pong buffer every 3000 values. The problem is
that from 3001-3400 value, for example, the sample
values are clearly not the signal values, but a value
which is 2, 4 or 8 times greater than the signal
value, as the third graph can show.

My question, what could be causing this bit shift in
the first values of each ping/pong buffers. Is it a
problem in the code of the ADC, EDMA initialization,
memory allocation, etc.?

Any help will be greatly appreciated.

Att.,

Juan A. Torres-Rosario __________________________________

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Reply by Andrew Elder ●May 27, 20042004-05-27

Juan,

EDMA configuration won't affect sample bit alignment.

I would double check the McBSP configuration and setup matches the clocking of
the ADC.

Also, be aware that if you are using DRAM memory buffers for the EDMA
destination and have internal cache enabled, you have to take care to do a cache
flush after processing a buffer of data.

- Andrew E.

At 07:10 PM 5/26/2004 -0700, Juan Torres wrote:
>Hi c6x Group,
>
>I am working with the C6711 DSK (150 MHz clock) and a
>THS1206 Daughter Board, which has 4 channels and a
>maximum sampling frequency of 6 MSPS for the 4
>channels. I was able to produce a code to acquire data
>from this ADC for 4 channels with sampling frequency
>of 25 kHz per channel using pingpong buffering scheme
>and EDMA transfer. The problem that I am having is
>that the first values of every buffer processed are
>not the values of the signal. Ironically, these values
>have the same form of the signal but the are bigger by
>a factor of 2 or a multiple of 2 (as if a bit has been
>added to the right side of the value).
>
>For example, in this e-mail, I am showing 3 graphs.
>One of the graphs shows a signal which represents the
>result of adding the 4 channels, which are receiving a
>purely sinosioidal signal with the same phase. A
>second graph shows a zoom of the signal. The width of
>each ping/pong buffer is 12000 shorts (3000 per
>channel). Since the output value is the sum of the 4
>channels, the output buffer shows the result of a
>ping/pong buffer every 3000 values. The problem is
>that from 3001-3400 value, for example, the sample
>values are clearly not the signal values, but a value
>which is 2, 4 or 8 times greater than the signal
>value, as the third graph can show.
>
>My question, what could be causing this bit shift in
>the first values of each ping/pong buffers. Is it a
>problem in the code of the ADC, EDMA initialization,
>memory allocation, etc.?
>
>Any help will be greatly appreciated.
>
>Att.,
>
>Juan A. Torres-Rosario >__________________________________
>
>_____________________________________
>Note: If you do a simple "reply" with your email client, only the author of
this message will receive your answer. You need to do a "reply all" if you want
your answer to be distributed to the entire group.
>
>_____________________________________
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>
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>
>Yahoo! Groups Links >
Reply by Amrut Kunte ●May 28, 20042004-05-28
Hello Andrew,
I am also facing a problem but while doing QDMA.
Could you please clarify why is the need for Cache Flush after DMA.
Can the Caching [its a sort of automatic DMA] co-exist with QDMA
requests?

Regards,
Amrut --- Andrew Elder <> wrote: >
> Juan,
>
> EDMA configuration won't affect sample bit alignment.
>
> I would double check the McBSP configuration and setup matches the
> clocking of the ADC.
>
> Also, be aware that if you are using DRAM memory buffers for the EDMA
> destination and have internal cache enabled, you have to take care to
> do a cache flush after processing a buffer of data.
>
> - Andrew E.
>
> At 07:10 PM 5/26/2004 -0700, Juan Torres wrote:
> >Hi c6x Group,
> >
> >I am working with the C6711 DSK (150 MHz clock) and a
> >THS1206 Daughter Board, which has 4 channels and a
> >maximum sampling frequency of 6 MSPS for the 4
> >channels. I was able to produce a code to acquire data
> >from this ADC for 4 channels with sampling frequency
> >of 25 kHz per channel using pingpong buffering scheme
> >and EDMA transfer. The problem that I am having is
> >that the first values of every buffer processed are
> >not the values of the signal. Ironically, these values
> >have the same form of the signal but the are bigger by
> >a factor of 2 or a multiple of 2 (as if a bit has been
> >added to the right side of the value).
> >
> >For example, in this e-mail, I am showing 3 graphs.
> >One of the graphs shows a signal which represents the
> >result of adding the 4 channels, which are receiving a
> >purely sinosioidal signal with the same phase. A
> >second graph shows a zoom of the signal. The width of
> >each ping/pong buffer is 12000 shorts (3000 per
> >channel). Since the output value is the sum of the 4
> >channels, the output buffer shows the result of a
> >ping/pong buffer every 3000 values. The problem is
> >that from 3001-3400 value, for example, the sample
> >values are clearly not the signal values, but a value
> >which is 2, 4 or 8 times greater than the signal
> >value, as the third graph can show.
> >
> >My question, what could be causing this bit shift in
> >the first values of each ping/pong buffers. Is it a
> >problem in the code of the ADC, EDMA initialization,
> >memory allocation, etc.?
> >
> >Any help will be greatly appreciated.
> >
> >Att.,
> >
> >Juan A. Torres-Rosario
> >
> >
> >
> >
> >
> >__________________________________
> >
> >_____________________________________
> >Note: If you do a simple "reply" with your email client, only the
> author of this message will receive your answer. You need to do a
> "reply all" if you want your answer to be distributed to the entire
> group.
> >
> >_____________________________________
> >About this discussion group:
> >
> >To Join: Send an email to
> >
> >To Post: Send an email to
> >
> >To Leave: Send an email to
> >
> >Archives: http://www.yahoogroups.com/group/c6x
> >
> >Other Groups: http://www.dsprelated.com
> >
> >Yahoo! Groups Links
> >
> >
> >
> >
> >
> >
> _____________________________________
> Note: If you do a simple "reply" with your email client, only the
> author of this message will receive your answer. You need to do a
> "reply all" if you want your answer to be distributed to the entire
> group.
>
> _____________________________________
> About this discussion group:
>
> To Join: Send an email to
>
> To Post: Send an email to
>
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> Archives: http://www.yahoogroups.com/group/c6x
>
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>
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===== ________________________________________________________________________
Yahoo! India Matrimony: Find your partner online.
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Reply by dspnuts ●June 2, 20042004-06-02
Hi Amrut, I'll try to add a few notes here to see if helps,

memory addresses that are in external memory (and have corresponding
Memory Atttibute Register (MAR) configured) will be cached by the L1
(and L2 if enabled) caches when the 'cpu' touches those addresses.

modifications to those addresses will be made to the cached copy of
those memory locations and will only be written back to the physical
memory, when the cache line is written back.

The dma always works (reads/writes) from the physical memory
location (and not the cached copy) and doesn't know that there may
be modified data in the cache - any cached data that you want to be
picked up by the dma should first be written back before the dma job
is triggered.

... on the other side, if reading from memory that will be touched
by the dma, the cached lines should be invalidated, such that the
new data in external memory will be re-read into the cache.

> back to your question : QDMA is user triggered dma, so applies
the same way. If you are touching buffers in external memory (that
are cacheable via MAR) with both the CPU and DMA, you need to take
care of the cache coherency.

raj

--- In , Amrut Kunte <amrut_kunte@y...> wrote:
> Hello Andrew,
> I am also facing a problem but while doing QDMA.
> Could you please clarify why is the need for Cache Flush after DMA.
> Can the Caching [its a sort of automatic DMA] co-exist with QDMA
> requests?
>
> Regards,
> Amrut > --- Andrew Elder <andrew_elder@b...> wrote: >
> > Juan,
> >
> > EDMA configuration won't affect sample bit alignment.
> >
> > I would double check the McBSP configuration and setup matches
the
> > clocking of the ADC.
> >
> > Also, be aware that if you are using DRAM memory buffers for the
EDMA
> > destination and have internal cache enabled, you have to take
care to
> > do a cache flush after processing a buffer of data.
> >
> > - Andrew E.
> >
> > At 07:10 PM 5/26/2004 -0700, Juan Torres wrote:
> > >Hi c6x Group,
> > >
> > >I am working with the C6711 DSK (150 MHz clock) and a
> > >THS1206 Daughter Board, which has 4 channels and a
> > >maximum sampling frequency of 6 MSPS for the 4
> > >channels. I was able to produce a code to acquire data
> > >from this ADC for 4 channels with sampling frequency
> > >of 25 kHz per channel using pingpong buffering scheme
> > >and EDMA transfer. The problem that I am having is
> > >that the first values of every buffer processed are
> > >not the values of the signal. Ironically, these values
> > >have the same form of the signal but the are bigger by
> > >a factor of 2 or a multiple of 2 (as if a bit has been
> > >added to the right side of the value).
> > >
> > >For example, in this e-mail, I am showing 3 graphs.
> > >One of the graphs shows a signal which represents the
> > >result of adding the 4 channels, which are receiving a
> > >purely sinosioidal signal with the same phase. A
> > >second graph shows a zoom of the signal. The width of
> > >each ping/pong buffer is 12000 shorts (3000 per
> > >channel). Since the output value is the sum of the 4
> > >channels, the output buffer shows the result of a
> > >ping/pong buffer every 3000 values. The problem is
> > >that from 3001-3400 value, for example, the sample
> > >values are clearly not the signal values, but a value
> > >which is 2, 4 or 8 times greater than the signal
> > >value, as the third graph can show.
> > >
> > >My question, what could be causing this bit shift in
> > >the first values of each ping/pong buffers. Is it a
> > >problem in the code of the ADC, EDMA initialization,
> > >memory allocation, etc.?
> > >
> > >Any help will be greatly appreciated.
> > >
> > >Att.,
> > >
> > >Juan A. Torres-Rosario
> > >trutano@y...
> > >
> > >
> > >
> > >
> > >__________________________________
> > >
> > >_____________________________________
> > >Note: If you do a simple "reply" with your email client, only
the
> > author of this message will receive your answer. You need to do
a
> > "reply all" if you want your answer to be distributed to the
entire
> > group.
> > >
> > >_____________________________________
> > >About this discussion group:
> > >
> > >To Join: Send an email to
> > >
> > >To Post: Send an email to
> > >
> > >To Leave: Send an email to
> > >
> > >Archives: http://www.yahoogroups.com/group/c6x
> > >
> > >Other Groups: http://www.dsprelated.com
> > >
> > >Yahoo! Groups Links
> > >
> > >
> > >
> > >
> > >
> > >
> >
> >
> >
> > _____________________________________
> > Note: If you do a simple "reply" with your email client, only the
> > author of this message will receive your answer. You need to do
a
> > "reply all" if you want your answer to be distributed to the
entire
> > group.
> >
> > _____________________________________
> > About this discussion group:
> >
> > To Join: Send an email to
> >
> > To Post: Send an email to
> >
> > To Leave: Send an email to
> >
> > Archives: http://www.yahoogroups.com/group/c6x
> >
> > Other Groups: http://www.dsprelated.com
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
>
> ===== >
_____________________________________________________________________
___
> Yahoo! India Matrimony: Find your partner online.
http://yahoo.shaadi.com/india-matrimony/



Reply by Amrut Kunte ●June 3, 20042004-06-03
Hello,
Thanks, You are right.
I read this in the spru656. Cache coherency is programmer's
responsibility.

Am I right in saying that QDMA is just one channel which means that
only one "DAT_copy" can be issued at a time. And there is no way to
start multiple QDMA transfers at a time?

Also, why would anyone use EDMA[complex] for memory to memory transfers
when QDMA[simple] is available?

rgds,
Amrut --- dspnuts <> wrote: > Hi Amrut, I'll try to add
a few notes here to see if helps,
>
> memory addresses that are in external memory (and have corresponding
> Memory Atttibute Register (MAR) configured) will be cached by the L1
> (and L2 if enabled) caches when the 'cpu' touches those addresses.
>
> modifications to those addresses will be made to the cached copy of
> those memory locations and will only be written back to the physical
> memory, when the cache line is written back.
>
> The dma always works (reads/writes) from the physical memory
> location (and not the cached copy) and doesn't know that there may
> be modified data in the cache - any cached data that you want to be
> picked up by the dma should first be written back before the dma job
> is triggered.
>
> ... on the other side, if reading from memory that will be touched
> by the dma, the cached lines should be invalidated, such that the
> new data in external memory will be re-read into the cache.
>
> > back to your question : QDMA is user triggered dma, so applies
> the same way. If you are touching buffers in external memory (that
> are cacheable via MAR) with both the CPU and DMA, you need to take
> care of the cache coherency.
>
> raj
>
> --- In , Amrut Kunte <amrut_kunte@y...> wrote:
> > Hello Andrew,
> > I am also facing a problem but while doing QDMA.
> > Could you please clarify why is the need for Cache Flush after DMA.
> > Can the Caching [its a sort of automatic DMA] co-exist with QDMA
> > requests?
> >
> > Regards,
> > Amrut
> >
> >
> > --- Andrew Elder <andrew_elder@b...> wrote: >
> > > Juan,
> > >
> > > EDMA configuration won't affect sample bit alignment.
> > >
> > > I would double check the McBSP configuration and setup matches
> the
> > > clocking of the ADC.
> > >
> > > Also, be aware that if you are using DRAM memory buffers for the
> EDMA
> > > destination and have internal cache enabled, you have to take
> care to
> > > do a cache flush after processing a buffer of data.
> > >
> > > - Andrew E.
> > >
> > > At 07:10 PM 5/26/2004 -0700, Juan Torres wrote:
> > > >Hi c6x Group,
> > > >
> > > >I am working with the C6711 DSK (150 MHz clock) and a
> > > >THS1206 Daughter Board, which has 4 channels and a
> > > >maximum sampling frequency of 6 MSPS for the 4
> > > >channels. I was able to produce a code to acquire data
> > > >from this ADC for 4 channels with sampling frequency
> > > >of 25 kHz per channel using pingpong buffering scheme
> > > >and EDMA transfer. The problem that I am having is
> > > >that the first values of every buffer processed are
> > > >not the values of the signal. Ironically, these values
> > > >have the same form of the signal but the are bigger by
> > > >a factor of 2 or a multiple of 2 (as if a bit has been
> > > >added to the right side of the value).
> > > >
> > > >For example, in this e-mail, I am showing 3 graphs.
> > > >One of the graphs shows a signal which represents the
> > > >result of adding the 4 channels, which are receiving a
> > > >purely sinosioidal signal with the same phase. A
> > > >second graph shows a zoom of the signal. The width of
> > > >each ping/pong buffer is 12000 shorts (3000 per
> > > >channel). Since the output value is the sum of the 4
> > > >channels, the output buffer shows the result of a
> > > >ping/pong buffer every 3000 values. The problem is
> > > >that from 3001-3400 value, for example, the sample
> > > >values are clearly not the signal values, but a value
> > > >which is 2, 4 or 8 times greater than the signal
> > > >value, as the third graph can show.
> > > >
> > > >My question, what could be causing this bit shift in
> > > >the first values of each ping/pong buffers. Is it a
> > > >problem in the code of the ADC, EDMA initialization,
> > > >memory allocation, etc.?
> > > >
> > > >Any help will be greatly appreciated.
> > > >
> > > >Att.,
> > > >
> > > >Juan A. Torres-Rosario
> > > >trutano@y...
> > > >
> > > >
> > > >
> > > >
> > > >__________________________________
> > > >
> > > >_____________________________________
> > > >Note: If you do a simple "reply" with your email client, only
> the
> > > author of this message will receive your answer. You need to do
> a
> > > "reply all" if you want your answer to be distributed to the
> entire
> > > group.
> > > >
> > > >_____________________________________
> > > >About this discussion group:
> > > >
> > > >To Join: Send an email to
> > > >
> > > >To Post: Send an email to
> > > >
> > > >To Leave: Send an email to
> > > >
> > > >Archives: http://www.yahoogroups.com/group/c6x
> > > >
> > > >Other Groups: http://www.dsprelated.com
> > > >
> > > >Yahoo! Groups Links
> > > >
> > > >
> > > >
> > > >
> > > >
> > > >
> > >
> > >
> > >
> > > _____________________________________
> > > Note: If you do a simple "reply" with your email client, only the
> > > author of this message will receive your answer. You need to do
> a
> > > "reply all" if you want your answer to be distributed to the
> entire
> > > group.
> > >
> > > _____________________________________
> > > About this discussion group:
> > >
> > > To Join: Send an email to
> > >
> > > To Post: Send an email to
> > >
> > > To Leave: Send an email to
> > >
> > > Archives: http://www.yahoogroups.com/group/c6x
> > >
> > > Other Groups: http://www.dsprelated.com
> > >
> > > Yahoo! Groups Links
> > >
> > >
> > >
> > >
> > >
> >
> > =====
> >
> >
> >
> _____________________________________________________________________
> ___
> > Yahoo! India Matrimony: Find your partner online.
> http://yahoo.shaadi.com/india-matrimony/ >
>
> _____________________________________
> Note: If you do a simple "reply" with your email client, only the
> author of this message will receive your answer. You need to do a
> "reply all" if you want your answer to be distributed to the entire
> group.
>
> _____________________________________
> About this discussion group:
>
> To Join: Send an email to
>
> To Post: Send an email to
>
> To Leave: Send an email to
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>
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>
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=== message truncated ===

===== ________________________________________________________________________
Yahoo! India Matrimony: Find your partner online.
http://yahoo.shaadi.com/india-matrimony/


Reply by Amrut Kunte ●June 3, 20042004-06-03
Hello,
Is there a gap between Simulator [Flat Memeory model] figures and All
Internal memory operation figures on hardware?

If yes, what factor creates the gap?

thanks.
Amrut

===== ________________________________________________________________________
Yahoo! India Matrimony: Find your partner online.
http://yahoo.shaadi.com/india-matrimony/

Reply by dspnuts ●June 6, 20042004-06-06
Hi Amrut,

In my understanding, QDMA is just an easy way for the cpu to issue a
transfer request to the EDMA engine. The EDMA is the block that actually
performs the transfer. I think the EDMA on 64x has 4 priority queues, on
which a num of transfers can be submitted. The QDMA can issue requests to
the EDMA on any of these queues. Multiple QDMA requests can be made without
waiting for completion of the previous request (assuming the queues are not
full).

The DAT_xxxx module, is a C wrapper call that issues QDMA requests. Upon
opening the DAT module (DAT_open(...)), the priority queue for these QDMA
requests to issued on is specified, hence DAT always makes QDMA requests on
the same priority queue.

DAT_copy API returns an Id so that you can wait for the request to complete,
using DAT_wait();

Requests made on the same queue will complete serially, hence you should be
able to issue back-to-back DAT_copy's and simply wait on the last Id and be
sure that previous DAT copies will have completed.

id = DAT_copy();
id = DAT_copy();
id = DAT_copy();
id = DAT_copy();
DAT_wait(id);

Hope this helps,
raj ----- Original Message -----
From: "Amrut Kunte" <>
To: <>
Sent: Thursday, June 03, 2004 4:18 PM
Subject: Re: [c6x] Re: Problems with EDMA transfer > Hello,
> Thanks, You are right.
> I read this in the spru656. Cache coherency is programmer's
> responsibility.
>
> Am I right in saying that QDMA is just one channel which means that
> only one "DAT_copy" can be issued at a time. And there is no way to
> start multiple QDMA transfers at a time?
>
> Also, why would anyone use EDMA[complex] for memory to memory transfers
> when QDMA[simple] is available?
>
> rgds,
> Amrut > --- dspnuts <> wrote: > Hi Amrut, I'll try to add
> a few notes here to see if helps,
> >
> > memory addresses that are in external memory (and have corresponding
> > Memory Atttibute Register (MAR) configured) will be cached by the L1
> > (and L2 if enabled) caches when the 'cpu' touches those addresses.
> >
> > modifications to those addresses will be made to the cached copy of
> > those memory locations and will only be written back to the physical
> > memory, when the cache line is written back.
> >
> > The dma always works (reads/writes) from the physical memory
> > location (and not the cached copy) and doesn't know that there may
> > be modified data in the cache - any cached data that you want to be
> > picked up by the dma should first be written back before the dma job
> > is triggered.
> >
> > ... on the other side, if reading from memory that will be touched
> > by the dma, the cached lines should be invalidated, such that the
> > new data in external memory will be re-read into the cache.
> >
> > > back to your question : QDMA is user triggered dma, so applies
> > the same way. If you are touching buffers in external memory (that
> > are cacheable via MAR) with both the CPU and DMA, you need to take
> > care of the cache coherency.
> >
> > raj
> >
> > --- In , Amrut Kunte <amrut_kunte@y...> wrote:
> > > Hello Andrew,
> > > I am also facing a problem but while doing QDMA.
> > > Could you please clarify why is the need for Cache Flush after DMA.
> > > Can the Caching [its a sort of automatic DMA] co-exist with QDMA
> > > requests?
> > >
> > > Regards,
> > > Amrut
> > >
> > >
> > > --- Andrew Elder <andrew_elder@b...> wrote: >
> > > > Juan,
> > > >
> > > > EDMA configuration won't affect sample bit alignment.
> > > >
> > > > I would double check the McBSP configuration and setup matches
> > the
> > > > clocking of the ADC.
> > > >
> > > > Also, be aware that if you are using DRAM memory buffers for the
> > EDMA
> > > > destination and have internal cache enabled, you have to take
> > care to
> > > > do a cache flush after processing a buffer of data.
> > > >
> > > > - Andrew E.
> > > >
> > > > At 07:10 PM 5/26/2004 -0700, Juan Torres wrote:
> > > > >Hi c6x Group,
> > > > >
> > > > >I am working with the C6711 DSK (150 MHz clock) and a
> > > > >THS1206 Daughter Board, which has 4 channels and a
> > > > >maximum sampling frequency of 6 MSPS for the 4
> > > > >channels. I was able to produce a code to acquire data
> > > > >from this ADC for 4 channels with sampling frequency
> > > > >of 25 kHz per channel using pingpong buffering scheme
> > > > >and EDMA transfer. The problem that I am having is
> > > > >that the first values of every buffer processed are
> > > > >not the values of the signal. Ironically, these values
> > > > >have the same form of the signal but the are bigger by
> > > > >a factor of 2 or a multiple of 2 (as if a bit has been
> > > > >added to the right side of the value).
> > > > >
> > > > >For example, in this e-mail, I am showing 3 graphs.
> > > > >One of the graphs shows a signal which represents the
> > > > >result of adding the 4 channels, which are receiving a
> > > > >purely sinosioidal signal with the same phase. A
> > > > >second graph shows a zoom of the signal. The width of
> > > > >each ping/pong buffer is 12000 shorts (3000 per
> > > > >channel). Since the output value is the sum of the 4
> > > > >channels, the output buffer shows the result of a
> > > > >ping/pong buffer every 3000 values. The problem is
> > > > >that from 3001-3400 value, for example, the sample
> > > > >values are clearly not the signal values, but a value
> > > > >which is 2, 4 or 8 times greater than the signal
> > > > >value, as the third graph can show.
> > > > >
> > > > >My question, what could be causing this bit shift in
> > > > >the first values of each ping/pong buffers. Is it a
> > > > >problem in the code of the ADC, EDMA initialization,
> > > > >memory allocation, etc.?
> > > > >
> > > > >Any help will be greatly appreciated.
> > > > >
> > > > >Att.,
> > > > >
> > > > >Juan A. Torres-Rosario
> > > > >trutano@y...
> > > > >
> > > > >
> > > > >
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Reply by Amrut Kunte ●June 7, 20042004-06-07
Thanks,
Multiple DAT_copy issues do work, but I am facing a problem.
While waiting the DAT_wait(xfrID); gives wrong output, where as

/**********************/
while(DAT_busy(xfrID));

gives correct result. Any clue?

rgds
Amrut --- dspnuts <> wrote: > Hi Amrut,
>
> In my understanding, QDMA is just an easy way for the cpu to issue a
> transfer request to the EDMA engine. The EDMA is the block that
> actually
> performs the transfer. I think the EDMA on 64x has 4 priority
> queues, on
> which a num of transfers can be submitted. The QDMA can issue
> requests to
> the EDMA on any of these queues. Multiple QDMA requests can be made
> without
> waiting for completion of the previous request (assuming the queues
> are not
> full).
>
> The DAT_xxxx module, is a C wrapper call that issues QDMA requests.
> Upon
> opening the DAT module (DAT_open(...)), the priority queue for these
> QDMA
> requests to issued on is specified, hence DAT always makes QDMA
> requests on
> the same priority queue.
>
> DAT_copy API returns an Id so that you can wait for the request to
> complete,
> using DAT_wait();
>
> Requests made on the same queue will complete serially, hence you
> should be
> able to issue back-to-back DAT_copy's and simply wait on the last Id
> and be
> sure that previous DAT copies will have completed.
>
> id = DAT_copy();
> id = DAT_copy();
> id = DAT_copy();
> id = DAT_copy();
> DAT_wait(id);
>
> Hope this helps,
> raj > ----- Original Message -----
> From: "Amrut Kunte" <>
> To: <>
> Sent: Thursday, June 03, 2004 4:18 PM
> Subject: Re: [c6x] Re: Problems with EDMA transfer > > Hello,
> > Thanks, You are right.
> > I read this in the spru656. Cache coherency is programmer's
> > responsibility.
> >
> > Am I right in saying that QDMA is just one channel which means that
> > only one "DAT_copy" can be issued at a time. And there is no way to
> > start multiple QDMA transfers at a time?
> >
> > Also, why would anyone use EDMA[complex] for memory to memory
> transfers
> > when QDMA[simple] is available?
> >
> > rgds,
> > Amrut
> >
> >
> > --- dspnuts <> wrote: > Hi Amrut, I'll try to
> add
> > a few notes here to see if helps,
> > >
> > > memory addresses that are in external memory (and have
> corresponding
> > > Memory Atttibute Register (MAR) configured) will be cached by the
> L1
> > > (and L2 if enabled) caches when the 'cpu' touches those
> addresses.
> > >
> > > modifications to those addresses will be made to the cached copy
> of
> > > those memory locations and will only be written back to the
> physical
> > > memory, when the cache line is written back.
> > >
> > > The dma always works (reads/writes) from the physical memory
> > > location (and not the cached copy) and doesn't know that there
> may
> > > be modified data in the cache - any cached data that you want to
> be
> > > picked up by the dma should first be written back before the dma
> job
> > > is triggered.
> > >
> > > ... on the other side, if reading from memory that will be
> touched
> > > by the dma, the cached lines should be invalidated, such that the
> > > new data in external memory will be re-read into the cache.
> > >
> > > > back to your question : QDMA is user triggered dma, so applies
> > > the same way. If you are touching buffers in external memory
> (that
> > > are cacheable via MAR) with both the CPU and DMA, you need to
> take
> > > care of the cache coherency.
> > >
> > > raj
> > >
> > > --- In , Amrut Kunte <amrut_kunte@y...> wrote:
> > > > Hello Andrew,
> > > > I am also facing a problem but while doing QDMA.
> > > > Could you please clarify why is the need for Cache Flush after
> DMA.
> > > > Can the Caching [its a sort of automatic DMA] co-exist with
> QDMA
> > > > requests?
> > > >
> > > > Regards,
> > > > Amrut
> > > >
> > > >
> > > > --- Andrew Elder <andrew_elder@b...> wrote: >
> > > > > Juan,
> > > > >
> > > > > EDMA configuration won't affect sample bit alignment.
> > > > >
> > > > > I would double check the McBSP configuration and setup
> matches
> > > the
> > > > > clocking of the ADC.
> > > > >
> > > > > Also, be aware that if you are using DRAM memory buffers for
> the
> > > EDMA
> > > > > destination and have internal cache enabled, you have to take
> > > care to
> > > > > do a cache flush after processing a buffer of data.
> > > > >
> > > > > - Andrew E.
> > > > >
> > > > > At 07:10 PM 5/26/2004 -0700, Juan Torres wrote:
> > > > > >Hi c6x Group,
> > > > > >
> > > > > >I am working with the C6711 DSK (150 MHz clock) and a
> > > > > >THS1206 Daughter Board, which has 4 channels and a
> > > > > >maximum sampling frequency of 6 MSPS for the 4
> > > > > >channels. I was able to produce a code to acquire data
> > > > > >from this ADC for 4 channels with sampling frequency
> > > > > >of 25 kHz per channel using pingpong buffering scheme
> > > > > >and EDMA transfer. The problem that I am having is
> > > > > >that the first values of every buffer processed are
> > > > > >not the values of the signal. Ironically, these values
> > > > > >have the same form of the signal but the are bigger by
> > > > > >a factor of 2 or a multiple of 2 (as if a bit has been
> > > > > >added to the right side of the value).
> > > > > >
> > > > > >For example, in this e-mail, I am showing 3 graphs.
> > > > > >One of the graphs shows a signal which represents the
> > > > > >result of adding the 4 channels, which are receiving a
> > > > > >purely sinosioidal signal with the same phase. A
> > > > > >second graph shows a zoom of the signal. The width of
> > > > > >each ping/pong buffer is 12000 shorts (3000 per
> > > > > >channel). Since the output value is the sum of the 4
> > > > > >channels, the output buffer shows the result of a
> > > > > >ping/pong buffer every 3000 values. The problem is
> > > > > >that from 3001-3400 value, for example, the sample
> > > > > >values are clearly not the signal values, but a value
> > > > > >which is 2, 4 or 8 times greater than the signal
> > > > > >value, as the third graph can show.
> > > > > >
> > > > > >My question, what could be causing this bit shift in
> > > > > >the first values of each ping/pong buffers. Is it a
> > > > > >problem in the code of the ADC, EDMA initialization,
> > > > > >memory allocation, etc.?
> > > > > >
> > > > > >Any help will be greatly appreciated.
> > > > > >
> > > > > >Att.,
> > > > > >
> > > > > >Juan A. Torres-Rosario
> > > > > >trutano@y...
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >__________________________________
> > > > > >
> > > > > >_____________________________________
> > > > > >Note: If you do a simple "reply" with your email client,
> only
> > > the
> > > > > author of this message will receive your answer. You need to
> do
> > > a
> > > > > "reply all" if you want your answer to be distributed to the
> > > entire
> > > > > group.
> > > > > >
> > > > > >_____________________________________
>
=== message truncated ===

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Reply by Amrut Kunte ●June 7, 20042004-06-07
What is the measure of difference between Flat Memory Operation figures
obtained from the simulator & all internal memory operation [i.e. all
memory in L2] on hardware?

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