L2 Cache Profiling
I'm trying to improve the performance of my code, so I decides to test the L2 cache on my 6416 board. To configure the cache I use the DSP/BIOS config program. Now I did some profiling using the C6416 Device Cycle Accurate Simulator. The profile summary says, that there are many cache accesses, but exactly 100% L2 cache misses. How could this be possible?