I have refered to SPRA433D(TMS320C6000 EMIF-to-External SDRAM
Interface.pdf). It's said that C620x/C670x' can interface with 1 Meg x
32 x 4 banks SDRAM .While dealing with the address shifting. The SDWID
bit in SDCTL seems to tell us that C6000's EMIF only support 8-bit or
16-bit width SDRAM. So when interfacing 32-bit-width SDRAM with C6205.
How can i deal with the address shifting?
Any help will be highly appreciated!!!
How to interface 32-bit-width SDRAM with C6205
Started by ●June 1, 2005
Reply by ●June 2, 20052005-06-02
There must be some confusion over the meaning of this bit. it has
nothing to do with x8, x16 or x32. it has to do with the geometry of the
SDRAM used - specifically column width. the info below is from TI's
EMIF documentation.
mikedunn
SDWID SDRAM column width select (C620x/C670x)
SDWID = 0: 9 column address pins (512 elements per row)
SDWID = 1: 8 column address pins (256 elements per row)
xsws5638 <x...@yahoo.com.cn> wrote:
I have refered to SPRA433D(TMS320C6000 EMIF-to-External SDRAM
Interface.pdf). It's said that C620x/C670x' can interface with 1 Meg x
32 x 4 banks SDRAM .While dealing with the address shifting. The SDWID
bit in SDCTL seems to tell us that C6000's EMIF only support 8-bit or
16-bit width SDRAM. So when interfacing 32-bit-width SDRAM with C6205.
How can i deal with the address shifting?
Any help will be highly appreciated!!!
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