First of all thanks for the suggestions.
Here are few more observations about the problem.
When SDRAM is enabled and refresh is happening, there
is no problem with UART until i would't write onto
SDRAM.
If i read SDRAM. it has no effect. UART works
normally.
Once I write onto SDRAM, UART gets currupted.
If i write less no of bytes, say 10, it some times do
not disturb uart, but sometimes it does.
If i write more no of bytes it always disturbs.
This phenomonon is irrespective of location within
SDRAM.
Once again thanks for your help.
BHASKAR REDDY . N
Mysore
Cell: 9880 177365
__________________________________________________
SDRAM interface problem
Started by ●June 25, 2005
Reply by ●June 25, 20052005-06-25
Bhaskar-
> First of all thanks for the suggestions.
> Here are few more observations about the problem.
> When SDRAM is enabled and refresh is happening, there
> is no problem with UART until i would't write onto
> SDRAM.
> If i read SDRAM. it has no effect. UART works
> normally.
> Once I write onto SDRAM, UART gets currupted.
> If i write less no of bytes, say 10, it some times do
> not disturb uart, but sometimes it does.
> If i write more no of bytes it always disturbs.
> This phenomonon is irrespective of location within
> SDRAM.
One suggestion is to temporarily OR a GPIO pin with /CE3 and connect to
/CS signal on your UART. When configuring your UART, set the GPIO pin low
so /CE3 can work normally.... but before writing to SDRAM, set the GPIO
pin to high.
This will tell you whether the UART is the problem or your timing between
SDRAM writes and async writes using /CE3 is the problem. If the UART is
*still* corrupted then somehow your UART is responding to /AWE even when
/CS is high.
Yes this is a bit of board re-work, but not too bad... hopefully you have
an unused OR-gate or unused CPLD pins you can use. The extra effort is a
small price to pay for a way to break this problem down and get a clear
view.
-Jeff
> First of all thanks for the suggestions.
> Here are few more observations about the problem.
> When SDRAM is enabled and refresh is happening, there
> is no problem with UART until i would't write onto
> SDRAM.
> If i read SDRAM. it has no effect. UART works
> normally.
> Once I write onto SDRAM, UART gets currupted.
> If i write less no of bytes, say 10, it some times do
> not disturb uart, but sometimes it does.
> If i write more no of bytes it always disturbs.
> This phenomonon is irrespective of location within
> SDRAM.
One suggestion is to temporarily OR a GPIO pin with /CE3 and connect to
/CS signal on your UART. When configuring your UART, set the GPIO pin low
so /CE3 can work normally.... but before writing to SDRAM, set the GPIO
pin to high.
This will tell you whether the UART is the problem or your timing between
SDRAM writes and async writes using /CE3 is the problem. If the UART is
*still* corrupted then somehow your UART is responding to /AWE even when
/CS is high.
Yes this is a bit of board re-work, but not too bad... hopefully you have
an unused OR-gate or unused CPLD pins you can use. The extra effort is a
small price to pay for a way to break this problem down and get a clear
view.
-Jeff
Reply by ●June 30, 20052005-06-30
check the refresh rate, Latency and the GCR. Best place is refer manf.
spec SDRAM
-
Bhaskar Reddy N <t...@yahoo.com> wrote:
Bhaskar Reddy N <t...@yahoo.com> wrote:
First of all thanks for the suggestions.
Here are few more observations about the problem.
When SDRAM is enabled and refresh is happening, there
is no problem with UART until i would't write onto
SDRAM.
If i read SDRAM. it has no effect. UART works
normally.
Once I write onto SDRAM, UART gets currupted.
If i write less no of bytes, say 10, it some times do
not disturb uart, but sometimes it does.
If i write more no of bytes it always disturbs.
This phenomonon is irrespective of location within
SDRAM.
Once again thanks for your help.
BHASKAR REDDY . N
Mysore
Cell: 9880 177365
__________________________________________________
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