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Avnet USB to C6713 DSK

Started by boin...@cse.uta.edu October 13, 2005

Hello,
I posted to the group during the summer with a question about Avnet's USB working with the C6713 DSK. I finally got the two working together. Nobody responded to my email with positive info so here is what I did.

I recompiled Avnet's example code for the c6416 DSK for the C6713 DSK with the minor changes of changing all the calls to the C6416bsl to the correcponding ones from C6713bsl.

First DSK6713_init() resets the SYSCLK3 to 75MHz and according to spraa13a to interface to the SX2 CE2 write hold should be at least 75ns. The maximum number of write hold clock cicles for the C6713 is 3 at 75MHz which is not enough. Transmited data to the DSK was correct but the data received by the PC was corrupted. I decreased SYSCLK3 to 40MHz and it worked fine.

Second DSK6713_init() also reconfigures the EMIF. you can either rebuild the library with the correct settings or reconfigure CE2 after calling DSK6713_init. Here is the EMIF_Config which worked for me:

EMIF_Config emifCfg1 = {
0x60 |
EMIF_FMKS(GBLCTL, NOHOLD, ENABLE) |
EMIF_FMKS(GBLCTL, CLK1EN, DISABLE) |
EMIF_FMKS(GBLCTL, CLK2EN, ENABLE),

EMIF_FMKS(CECTL, WRSETUP, DEFAULT) |
EMIF_FMKS(CECTL, WRSTRB, DEFAULT) |
EMIF_FMKS(CECTL, WRHLD, DEFAULT) |
EMIF_FMKS(CECTL, RDSETUP, DEFAULT) |
EMIF_FMKS(CECTL, TA, OF(2)) |
EMIF_FMKS(CECTL, RDSTRB, DEFAULT) |
EMIF_FMKS(CECTL, MTYPE, SDRAM32) |
EMIF_FMKS(CECTL, RDHLD, DEFAULT),

EMIF_FMKS(CECTL, WRSETUP, OF(0)) |
EMIF_FMKS(CECTL, WRSTRB, OF(8)) |
EMIF_FMKS(CECTL, WRHLD, OF(2)) |
EMIF_FMKS(CECTL, RDSETUP, OF(0)) |
EMIF_FMKS(CECTL, TA, OF(2)) |
EMIF_FMKS(CECTL, RDSTRB, OF(8)) |
EMIF_FMKS(CECTL, MTYPE, ASYNC8) |
EMIF_FMKS(CECTL, RDHLD, OF(2)),

/* CE2 hooked to SX2 */
EMIF_FMKS(CECTL, WRSETUP, OF(1)) |
EMIF_FMKS(CECTL, WRSTRB, OF(3)) |
EMIF_FMKS(CECTL, WRHLD, OF(3)) |
EMIF_FMKS(CECTL, RDSETUP, OF(1)) |
EMIF_FMKS(CECTL, TA, OF(1)) |
EMIF_FMKS(CECTL, RDSTRB, OF(3)) |
EMIF_FMKS(CECTL, MTYPE, ASYNC32) |
EMIF_FMKS(CECTL, RDHLD, OF(2)),

EMIF_FMKS(CECTL, WRSETUP, OF(2)) |
EMIF_FMKS(CECTL, WRSTRB, OF(10)) |
EMIF_FMKS(CECTL, WRHLD, OF(2)) |
EMIF_FMKS(CECTL, RDSETUP, OF(2)) |
EMIF_FMKS(CECTL, TA, OF(2)) |
EMIF_FMKS(CECTL, RDSTRB, OF(10)) |
EMIF_FMKS(CECTL, MTYPE, ASYNC32) |
EMIF_FMKS(CECTL, RDHLD, OF(2)),

EMIF_FMKS(SDCTL, SDBSZ, 4BANKS) |
EMIF_FMKS(SDCTL, SDRSZ, 12ROW) |
EMIF_FMKS(SDCTL, SDCSZ, 8COL) |
EMIF_FMKS(SDCTL, RFEN, ENABLE) |
EMIF_FMKS(SDCTL, INIT, YES) |
EMIF_FMKS(SDCTL, TRCD, OF(1)) |
EMIF_FMKS(SDCTL, TRP, OF(1)) |
EMIF_FMKS(SDCTL, TRC, OF(5)),

EMIF_FMKS(SDTIM, CNTR, OF(0)) |
EMIF_FMKS(SDTIM, PERIOD, OF(1400)),

EMIF_FMKS(SDEXT, WR2RD, OF(0)) |
EMIF_FMKS(SDEXT, WR2DEAC, OF(2)) |
EMIF_FMKS(SDEXT, WR2WR, OF(1)) |
EMIF_FMKS(SDEXT, R2WDQM, OF(1)) |
EMIF_FMKS(SDEXT, RD2WR, OF(0)) |
EMIF_FMKS(SDEXT, RD2DEAC, OF(1)) |
EMIF_FMKS(SDEXT, RD2RD, OF(0)) |
EMIF_FMKS(SDEXT, THZP, OF(2)) |
EMIF_FMKS(SDEXT, TWR, OF(1)) |
EMIF_FMKS(SDEXT, TRRD, OF(0)) |
EMIF_FMKS(SDEXT, TRAS, OF(4)) |
EMIF_FMKS(SDEXT, TCL, OF(1))
};

Todor