Hi all
I've read the datasheet of TMS320C6713. I don't known what is the
difference between MAP0 mode anf MAP1 ? How the memory of DSP are
addressed ? Which memory space is shared between program memory and
data memory , etc..
(The document of TI is difficult to known Sad
Anyone can explain they to me ?
Best regards
MAP memory of TMS320C6713?
Started by ●January 12, 2006
Reply by ●January 13, 20062006-01-13
muoinhohn,
--- muoinhohn <muoinhohn@muoi...> wrote:
> Hi all
>
> I've read the datasheet of TMS320C6713. I don't
> known what is the
> difference between MAP0 mode anf MAP1 ?
I am not sure what data sheet that you were reading.
Map0 and Map1 only apply to TMS320C620x and
TMS320C6701 devices.
> How the
> memory of DSP are
> addressed ? Which memory space is shared between
> program memory and
> data memory , etc..
The 6713 has internal memory beginning at add 0. It
can be used for program, data, or both.
> (The document of TI is difficult to known Sad
> Anyone can explain they to me ?
I do not understand the question.
mikedunn
>
> Best regards > c6x-unsubscribe@c6x-...
--- muoinhohn <muoinhohn@muoi...> wrote:
> Hi all
>
> I've read the datasheet of TMS320C6713. I don't
> known what is the
> difference between MAP0 mode anf MAP1 ?
I am not sure what data sheet that you were reading.
Map0 and Map1 only apply to TMS320C620x and
TMS320C6701 devices.
> How the
> memory of DSP are
> addressed ? Which memory space is shared between
> program memory and
> data memory , etc..
The 6713 has internal memory beginning at add 0. It
can be used for program, data, or both.
> (The document of TI is difficult to known Sad
> Anyone can explain they to me ?
I do not understand the question.
mikedunn
>
> Best regards > c6x-unsubscribe@c6x-...
Reply by ●January 13, 20062006-01-13
Dear Mikedunn
Thank you very much for your reponse. It's true. I've mistaken about the memory of C6713 and C670x.
In my kownledge, C6713's memory architecture is harvard that means it has program memory and data memory separeted. But maybe this is true only for the caches ? With the external memories, they are shared as like VonNeumann's architecture ?
Best regatds
