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SPI Initialization.

Started by SVS October 12, 2006
Dear Group Members,
I want to interface TMS320C6713 Processor with other Processors through SPI.
For simulating this DSPs McBSP I configured in SPI mode. SPI-0 is configured in Master Mode, and SPI-1 in Slave Mode. My intension is to transmit data through SPI0-Tx and receive from SPI-1 Rx.
Here I am explaining initialization procedure.
1) Configured SPI-0 in master mode
2) Configured SPI-1 slave mode
3) SPI Clock Frequency 7.5MHz(Core Freq 225MHz)
4) EDMA initializations for SPI-0 Tx(Channel 12)
5) EDMA initializations for SPI-1 Rx(Channel 15)
6) Enabling EDMA interrupt
7) Enabling SPI-1 Rx
8) Enabling SPI-0 Tx
For every SPI-0 Transmission I am getting EDMA Transmission complete interrupt (Ch-12) , but I am not getting EDMA Receive Interrupt
Regarding hardware connections I mapped
DX0->DR1
DR0->DX1
CLKX0->CLKX1
FSX0->FSX1( hardware DSK6713)
I observed that hardware connections are 100% ok! and SPI-0 Tx is working properly.
i am giving code details here
/************************main code***************************/

#define CHIP_6713 1
/* Inlcude files */
#include
#include /* CSL library */
#include /* DMA_SUPPORT */
#include /* EDMA_SUPPORT */
#include /* IRQ_SUPPORT */
#include /* MCBSP_SUPPORT */
#include "Spidefine.h"
/*--------*/
/* Global variables used in interrupt ISRs */
volatile int recv0_done = FALSE;
volatile int xmit0_done = FALSE;
volatile int recv1_done = FALSE;
volatile int xmit1_done = FALSE;

/*--------*/
/* Declare CSL objects */
MCBSP_Handle hMcbsp0,hMcbsp1; /* Handles for McBSP */
#if (DMA_SUPPORT)
DMA_Handle hDma1; /* Handles for DMA */
DMA_Handle hDma2;
#endif
#if (EDMA_SUPPORT) /* Handles for EDMA */
EDMA_Handle hEdma1,hEdma2,hEdma3,hEdma4;
EDMA_Handle hEdma;
EDMA_Handle hEdmadummy;
#endif
/*--------*/
/* External functions and function prototypes */
void init_mcbsp0_master(void); /* Function prototypes */
void init_mcbsp1_slave(void);
void set_interrupts_edma(void);
void EDMA_SPI_Tx(MCBSP_Handle McBSPChannel,EDMA_Handle hEdmaChannel,Uint32 *SourceAddress,Uint32 Count,Uint32 McBspNo);
void EDMA_SPI_Rx(MCBSP_Handle McBSPChannel,EDMA_Handle hEdmaChannel,Uint32 *DestinationAddress,Uint32 Count,Uint32 McBspNo);
void init_emif(void );
void init_cpld( void );
/* Inlcude the vector table to call the IRQ ISRs hookup */
extern far void vectors();
/*--------*/
/* main() */
/*--------*/
void
main(void)
{
static int xfer_type; /* Declaration of local variables */
static int xfer_size;
unsigned count;
/***********************************Transmit&ReceiveBuffers**********************/
static Uint32 edmaInbuff1[BUFFER_SIZE]; /* buffer for DMA supporting devices */
static Uint32 edmaOutbuff1[BUFFER_SIZE];
static Uint32 edmaInbuff2[BUFFER_SIZE]; /* buffer for EDMA supporting devices */
static Uint32 edmaOutbuff2[BUFFER_SIZE];
/*********************************************************************************/

IRQ_setVecs(vectors); /* point to the IRQ vector table */
/* initialize EMIF*/
init_emif( );
/*Init CPLD settings for enable normal McBSP*/
init_cpld( );
xfer_type = XFER_TYPE;
xfer_size = XFER_SIZE;
/* initialize Tx and Rx buffers*/
for(count=0;count {
edmaOutbuff1[count]= 0x01234567+ count;/* fill with some data*/
edmaInbuff1[count]=0;
edmaInbuff2[count]=0;
edmaOutbuff2[count] +(count);
}
/* initialize the CSL library */
CSL_init();
/*reset EDMA Channels*/
EDMA_resetAll();
/* configure SPI-0 as a master*/
init_mcbsp0_master();
/* configure SPI-1 as a slave*/
init_mcbsp1_slave();
/* open EDMA Channels*/
//hEdma1 = EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET);/* SPI-0 receive*/
hEdma2 = EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET);/* SPI-0 transmit*/
hEdma3 = EDMA_open(EDMA_CHA_REVT1, EDMA_OPEN_RESET);/*SPI-1 receive*/
// hEdma4 = EDMA_open(EDMA_CHA_XEVT1, EDMA_OPEN_RESET);/*SPI-1 transmit*/
#if 0
hEdmadummy = EDMA_allocTable(-1); /* Dynamically allocates PaRAM RAM table*/
EDMA_configArgs(hEdmadummy, /* Dummy or Terminating Table in PaRAM */
0x00000000, /* Terminate EDMA transfers by linking to */
0x00000000, /* this NULL table */
0x00000000,
0x00000000,
0x00000000,
0x00000000
);
#endif
/* Enable sample rate generator GRST=1 */
MCBSP_enableSrgr(hMcbsp0); /* Handle to SRGR */
MCBSP_enableSrgr(hMcbsp1);

#if (EDMA_SUPPORT) /* for EDMA supporting devices */
EDMA_clearPram(0x00000000); /* Clear PaRAM RAM of the EDMA */
set_interrupts_edma();
#endif

while(1)
{
int i = 0;
xmit0_done=0;
recv0_done=0;
recv1_done=0;
xmit1_done=0;
LED1_on;

//EDMA_link(hEdma2, hEdmadummy); /* Link terminating event to the EDMA event */
// EDMA_link(hEdma3, hEdmadummy); /* Link terminating event to the EDMA event */

/*enable SPI-1 Rx */
EDMA_SPI_Rx(hMcbsp1,hEdma3, edmaInbuff1,xfer_size, McBSP1 );
MCBSP_enableRcv(hMcbsp1);
for(i=0;i<2;i++);

/*enable SPI-0 Tx */
EDMA_SPI_Tx(hMcbsp0,hEdma2, edmaOutbuff1,xfer_size,McBSP0 );
/* enable Sample Rate genrator*/
MCBSP_enableXmt(hMcbsp0);
/* wait 2 cycles*/
for(i=0;i<2;i++);

while (!xmit0_done);
//while (!recv1_done);

/*reset EDMA Channels*/
EDMA_reset(hEdma2);//Reset EDMA Tx Channel
EDMA_reset(hEdma3);//Reset EDMA Rx Channel

LED2_on ;

}

} /* end main */

/*--------*/
/* set_interrupts_edma() */
/*--------*/
void /* Set the interrupts */
set_interrupts_edma(void) /* if the device supports EDMA */
{
IRQ_nmiEnable();
IRQ_globalEnable();
IRQ_reset(IRQ_EVT_EDMAINT);
IRQ_disable(IRQ_EVT_EDMAINT);
EDMA_intDisable(12); /* ch 12 for McBSP0 transmit event XEVT0 */
EDMA_intDisable(13); /* ch 13 for McBSP0 receive event REVT0 */
EDMA_intDisable(14); /* ch 14 for McBSP1 transmit event XEVT0 */
EDMA_intDisable(15); /* ch 15 for McBSP1 receive event REVT0 */
IRQ_clear(IRQ_EVT_EDMAINT);
EDMA_intClear(12);
EDMA_intClear(13);
EDMA_intClear(14);
EDMA_intClear(15);

IRQ_enable(IRQ_EVT_EDMAINT);
EDMA_intEnable(12);
EDMA_intEnable(13);
EDMA_intEnable(14);
EDMA_intEnable(15);
return;
}

void EDMA_SPI_Tx(MCBSP_Handle McBSPChannel,EDMA_Handle hEdmaChannel,\
Uint32 *SourceAddress,Uint32 Count,Uint32 McBspNo)
{
volatile Uint32 unTemp;
if(McBspNo ==1)
{
unTemp;
}
else
{
unTemp;
}
EDMA_clearPram(0x00000000);
EDMA_configArgs(hEdmaChannel,
#if(!C64_SUPPORT)
EDMA_OPT_RMK(
EDMA_OPT_PRI_LOW, /* High priority EDMA */
EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits */
EDMA_OPT_2DS_DEFAULT,
EDMA_OPT_SUM_INC, /* Source increment by element size */
EDMA_OPT_2DD_DEFAULT,
EDMA_OPT_DUM_DEFAULT,
EDMA_OPT_TCINT_YES, /* Enable Transfer Complete Interrupt */
EDMA_OPT_TCC_OF(unTemp), /* TCCINT = 0xC, XEVT0 */
EDMA_OPT_LINK_NO, /* Disable linking to NULL table */
EDMA_OPT_FS_NO
),
#endif

EDMA_SRC_RMK((Uint32)SourceAddress), /*src to edmaOutbuff */
EDMA_CNT_RMK(0,Count), /* set count equal to xfer_size */
EDMA_DST_RMK(MCBSP_ADDRH(McBSPChannel, DXR)), /* dst addr to DXR0 */
EDMA_IDX_RMK(0,0),
EDMA_RLD_RMK(0,0)
);
#if 0
hEdmadummy = EDMA_allocTable(-1); /* Dynamically allocates PaRAM RAM table*/
EDMA_configArgs(hEdmadummy, /* Dummy or Terminating Table in PaRAM */
0x00000000, /* Terminate EDMA transfers by linking to */
0x00000000, /* this NULL table */
0x00000000,
0x00000000,
0x00000000,
0x00000000
);
#endif
// EDMA_link(hEdma, hEdmadummy); /* Link terminating event to the EDMA event */

/* Enable EDMA channels */
EDMA_enableChannel(hEdmaChannel);
}
void EDMA_SPI_Rx(MCBSP_Handle McBSPChannel,EDMA_Handle hEdmaChannel,Uint32 *DestinationAddress,Uint32 Count,Uint32 McBspNo)
{
volatile Uint32 unTemp;
if(McBspNo ==1)
{
unTemp; /* for configuring EDMA EVENT*/
}
else
{
unTemp;
}
//EDMA_clearPram(0x00000000);
EDMA_configArgs(hEdmaChannel,
#if (!C64_SUPPORT)
EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH, /* High priority EDMA */
EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits */
EDMA_OPT_2DS_DEFAULT,
EDMA_OPT_SUM_DEFAULT,
EDMA_OPT_2DD_DEFAULT,
EDMA_OPT_DUM_INC, /* Destination increment by element size */
EDMA_OPT_TCINT_YES, /* Enable Transfer Complete Interrupt */
EDMA_OPT_TCC_OF(unTemp), /* TCCINT = 0xD, REVT0 */
EDMA_OPT_LINK_YES, /* Enable linking to NULL table */
EDMA_OPT_FS_NO
),
#endif
#if (C64_SUPPORT)
EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH, /* High priority EDMA */
EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits */
EDMA_OPT_2DS_DEFAULT,
EDMA_OPT_SUM_DEFAULT,
EDMA_OPT_2DD_DEFAULT,
EDMA_OPT_DUM_INC, /* Destination increment by element size */
EDMA_OPT_TCINT_YES, /* Enable Transfer Complete Interrupt */
EDMA_OPT_TCC_OF(unTemp), /* TCCINT = 0xD, REVT0 */
EDMA_OPT_TCCM_DEFAULT,
EDMA_OPT_ATCINT_DEFAULT,
EDMA_OPT_ATCC_DEFAULT,
EDMA_OPT_PDTS_DEFAULT,
EDMA_OPT_PDTD_DEFAULT,
EDMA_OPT_LINK_NO, /* Enable linking to NULL table */
EDMA_OPT_FS_NO
),
#endif
EDMA_SRC_RMK(MCBSP_ADDRH(McBSPChannel, DRR)), /*src to DRR1 */
EDMA_CNT_RMK(0,Count), /*set count equal to xfer_size */
EDMA_DST_RMK((Uint32)DestinationAddress), /* dst addr to edmaInbuff */
EDMA_IDX_RMK(0,0),
EDMA_RLD_RMK(0,0)
);
#if 0
hEdmadummy = EDMA_allocTable(-1); /* Dynamically allocates PaRAM RAM table*/
EDMA_configArgs(hEdmadummy, /* Dummy or Terminating Table in PaRAM */
0x00000000, /* Terminate EDMA transfers by linking to */
0x00000000, /* this NULL table */
0x00000000,
0x00000000,
0x00000000,
0x00000000
);
#endif
// EDMA_link(hEdma, hEdmadummy); /* Link terminating event to the EDMA event */

EDMA_enableChannel(hEdmaChannel); /* Enable EDMA channels */
}
/*--------*/
/* DMA DATA TRANSFER COMPLETION ISRs */
/*--------*/
interrupt void /* vecs.asm hooks this up to IRQ 11 */
c_int11(void) /* DMA ch2 */
{
xmit0_done = TRUE;
return;
}
interrupt void /* vecs.asm hooks this up to IRQ 09 */
c_int09(void) /* DMA ch1 */
{
recv0_done = TRUE;
return;
}
interrupt void /* vecs.asm hooks this up to IRQ 08 */
c_int08(void) /* for the EDMA */
{
#if (EDMA_SUPPORT)
if (EDMA_intTest(12))
{
xmit0_done = TRUE;
EDMA_intClear(12); /* clear CIPR bit so future interrupts can be recognized */

}
else if (EDMA_intTest( 13))
{
recv0_done = TRUE;
EDMA_intClear(13); /* clear CIPR bit so future interrupts can be recognized */
}
else if (EDMA_intTest( 14))
{
xmit1_done = TRUE;
EDMA_intClear(14); /* clear CIPR bit so future interrupts can be recognized */
}

else if (EDMA_intTest( 15))
{
recv1_done = TRUE;
EDMA_intClear(15); /* clear CIPR bit so future interrupts can be recognized */
}
#endif
return;
}
interrupt void
c_int14(void)
{
//TimerEventHandler();
asm (" nop; ");
return;
} /* end c_int14 */

void init_emif(void )
{

/* EMIF setup */
*(int *)EMIF_GCTL = 0x00000068;
*(int *)EMIF_CE0 = 0xffffbf33; // CE0 SDRAM
*(int *)EMIF_CE1 = 0x02208802; // CE1 Flash 8-bit
*(int *)EMIF_CE2 = 0x22a28a22; // CE2 Daughtercard 32-bit async
*(int *)EMIF_CE3 = 0x22a28a22; // CE3 Daughtercard 32-bit async
if (Get_Board_Rev == 2)
{
*(int *)EMIF_SDRAMCTL = 0x57115000; // SDRAM control (16 Mb)
}
else
{
*(int *)EMIF_SDRAMCTL = 0x47115000; // SDRAM control (8 Mb)
}
*(int *)EMIF_SDRAMTIM = 0x00000578; // SDRAM timing (refresh)
*(int *)EMIF_SDRAMEXT = 0x000a8529; // SDRAM Extension register
}

void init_cpld( void)
{
*(char*)CPLD_STAT = 0;
*(char*)CPLD_DC = 0;
*(char*)CPLD_MISC = 3; /* to enable Mcbsp -0,1*/
}

/**************************************end of file************************************************/

/***********************mcbsp initializations**************************************************/

/*--------*/
/* init_mcbsp0_master() */
/*--------*/
/* MCBSP Config structure */
/* Setup the MCBSP_0 as a master */
void
init_mcbsp0_master(void)
{
/
MCBSP_Config mcbspCfg0 = {
//0x00001000, /* spcr */ /*CLKSTPb*/
0x00001800, /*CLKSTPb*/
0x000100A0, /* rcr */
0x000100A0, /* xcr */
0x2000005f, /* srgr */ // 225/15= 15MHz
0x00000000, /* mcr */
0x00000000, /* rcer */
0x00000000, /* xcer */
0x00000A0C /* pcr */ /*CLKXP=1*/
};
hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);
MCBSP_config(hMcbsp0, &mcbspCfg0);

}

/*--------*/
/* init_mcbsp1_slave() */
/*--------*/
/* MCBSP Config structure */
/* Setup the MCBSP_1 as a slave */
void
init_mcbsp1_slave(void)
{
MCBSP_Config mcbspCfg1 = {
//0x00001000, /* spcr *//*CLKSTPb*/
0x00001800,
0x000000A0, /* rcr */
0x000000A0, /* xcr */
0x20000001, /* srgr */
0x00000000, /* mcr */
0x00000000, /* rcer */
0x00000000, /* xcer */
0x0000000C /* pcr */ /*CLKXP=1*/
};
hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
MCBSP_config(hMcbsp1, &mcbspCfg1);

}

/********************************************************************************************/

/*************************interrupt vector table******************************************/
********************************************************************************
* Copyright (C) 2000 Texas Instruments Incorporated.
* All Rights Reserved
*------
* FILENAME...... vecs.asm
* DATE CREATED.. 12/06/2000
* LAST MODIFIED. 12/06/2000
********************************************************************************
*------
* Global symbols defined here and exported out of this file
*------
.global _vectors
.global _vector0
.global _vector1
.global _vector2
.global _vector3
.global _vector4
.global _vector5
.global _vector6
.global _vector7
.global _c_int08 ; Hookup the c_int08 ISR in main() for EDMA
.global _c_int09 ; Hookup the c_int09 ISR in main() for DMA
.global _vector10
.global _c_int11 ; Hookup the c_int11 ISR in main() for DMA
.global _vector12
.global _vector13
.global _c_int14 ; Hookup the c_int14 ISR in main()
.global _vector15
*------
* Global symbols referenced in this file but defined somewhere else.
* Remember that your interrupt service routines need to be referenced here.
*------
.ref _c_int00
*------
* This is a macro that instantiates one entry in the interrupt service table.
*------
VEC_ENTRY .macro addr
STW B0,*--B15
MVKL addr,B0
MVKH addr,B0
B B0
LDW *B15++,B0
NOP 2
NOP
NOP
.endm

*------
* This is a dummy interrupt service routine used to initialize the IST.
*------
_vec_dummy:
B B3
NOP 5
*------
* This is the actual interrupt service table (IST). It is properly aligned and
* is located in the subsection .text:vecs. This means if you don't explicitly
* specify this section in your linker command file, it will default and link
* into the .text section. Remember to set the ISTP register to point to this
* table.
*------
.sect ".text:vecs"
.align 1024
_vectors:
_vector0: VEC_ENTRY _vec_dummy
_vector1: VEC_ENTRY _vec_dummy
_vector2: VEC_ENTRY _vec_dummy
_vector3: VEC_ENTRY _vec_dummy
_vector4: VEC_ENTRY _vec_dummy
_vector5: VEC_ENTRY _vec_dummy
_vector6: VEC_ENTRY _vec_dummy
_vector7: VEC_ENTRY _vec_dummy
_vector8: VEC_ENTRY _c_int08 ; Hookup the c_int08 ISR in main() for EDMA
_vector9: VEC_ENTRY _c_int09 ; Hookup the c_int09 ISR in main() for DMA
_vector10: VEC_ENTRY _vec_dummy
_vector11: VEC_ENTRY _c_int11 ; Hookup the c_int11 ISR in main() for DMA
_vector12: VEC_ENTRY _vec_dummy
_vector13: VEC_ENTRY _vec_dummy
_vector14: VEC_ENTRY _c_int14 ; Hookup the c_int14 ISR in main()
_vector15: VEC_ENTRY _vec_dummy
*------

********************************************************************************
* End of vecs.asm
********************************************************************************

I am requesting to guide in this regard,
Thanks
SVS
Sita-

> I want to interface TMS320C6713 Processor with other Processors through SPI.
> For simulating this DSPs McBSP I configured in SPI mode. SPI-0 is configured in Master Mode, and SPI-1 in Slave Mode. My intension is to transmit data through SPI0-Tx and receive from SPI-1 Rx.
> Here I am explaining initialization procedure.
> 1) Configured SPI-0 in master mode
> 2) Configured SPI-1 slave mode
> 3) SPI Clock Frequency 7.5MHz(Core Freq 225MHz)
> 4) EDMA initializations for SPI-0 Tx(Channel 12)
> 5) EDMA initializations for SPI-1 Rx(Channel 15)
> 6) Enabling EDMA interrupt
> 7) Enabling SPI-1 Rx
> 8) Enabling SPI-0 Tx
> For every SPI-0 Transmission I am getting EDMA Transmission complete interrupt (Ch-12) , but I am not getting EDMA Receive Interrupt
> Regarding hardware connections I mapped
> DX0->DR1
> DR0->DX1
> CLKX0->CLKX1
> FSX0->FSX1( hardware DSK6713)
> I observed that hardware connections are 100% ok! and SPI-0 Tx is working properly.

As this is simple DSP-to-DSP connection, I suggest first trying "basic mode", with
SPI mode not enabled, and one DSP as "master" driving clock and framesync with other
receiving.

If you can get this to work, then you will gain a lot of learning about McBSP + EDMA
configuration and function, and also give you a reference for SPI debug. Once it's
working and you have your interrupt and EDMA issues resolved, you should be able to
simply flip the SPI bits and still have functionality.

-Jeff

> i am giving code details here
> /************************main code***************************/
>
> #define CHIP_6713 1
> /* Inlcude files */
> #include
> #include /* CSL library */
> #include /* DMA_SUPPORT */
> #include /* EDMA_SUPPORT */
> #include /* IRQ_SUPPORT */
> #include /* MCBSP_SUPPORT */
> #include "Spidefine.h"
> /*--------*/
> /* Global variables used in interrupt ISRs */
> volatile int recv0_done = FALSE;
> volatile int xmit0_done = FALSE;
> volatile int recv1_done = FALSE;
> volatile int xmit1_done = FALSE;
>
> /*--------*/
> /* Declare CSL objects */
> MCBSP_Handle hMcbsp0,hMcbsp1; /* Handles for McBSP */
> #if (DMA_SUPPORT)
> DMA_Handle hDma1; /* Handles for DMA */
> DMA_Handle hDma2;
> #endif
> #if (EDMA_SUPPORT) /* Handles for EDMA */
> EDMA_Handle hEdma1,hEdma2,hEdma3,hEdma4;
> EDMA_Handle hEdma;
> EDMA_Handle hEdmadummy;
> #endif
> /*--------*/
> /* External functions and function prototypes */
> void init_mcbsp0_master(void); /* Function prototypes */
> void init_mcbsp1_slave(void);
> void set_interrupts_edma(void);
> void EDMA_SPI_Tx(MCBSP_Handle McBSPChannel,EDMA_Handle hEdmaChannel,Uint32 *SourceAddress,Uint32 Count,Uint32 McBspNo);
> void EDMA_SPI_Rx(MCBSP_Handle McBSPChannel,EDMA_Handle hEdmaChannel,Uint32 *DestinationAddress,Uint32 Count,Uint32 McBspNo);
> void init_emif(void );
> void init_cpld( void );
> /* Inlcude the vector table to call the IRQ ISRs hookup */
> extern far void vectors();
> /*--------*/
> /* main() */
> /*--------*/
> void
> main(void)
> {
> static int xfer_type; /* Declaration of local variables */
> static int xfer_size;
> unsigned count;
> /***********************************Transmit&ReceiveBuffers**********************/
> static Uint32 edmaInbuff1[BUFFER_SIZE]; /* buffer for DMA supporting devices */
> static Uint32 edmaOutbuff1[BUFFER_SIZE];
> static Uint32 edmaInbuff2[BUFFER_SIZE]; /* buffer for EDMA supporting devices */
> static Uint32 edmaOutbuff2[BUFFER_SIZE];
> /*********************************************************************************/
>
> IRQ_setVecs(vectors); /* point to the IRQ vector table */
> /* initialize EMIF*/
> init_emif( );
> /*Init CPLD settings for enable normal McBSP*/
> init_cpld( );
> xfer_type = XFER_TYPE;
> xfer_size = XFER_SIZE;
> /* initialize Tx and Rx buffers*/
> for(count=0;count > {
> edmaOutbuff1[count]= 0x01234567+ count;/* fill with some data*/
> edmaInbuff1[count]=0;
> edmaInbuff2[count]=0;
> edmaOutbuff2[count] +(count);
> }
> /* initialize the CSL library */
> CSL_init();
> /*reset EDMA Channels*/
> EDMA_resetAll();
> /* configure SPI-0 as a master*/
> init_mcbsp0_master();
> /* configure SPI-1 as a slave*/
> init_mcbsp1_slave();
> /* open EDMA Channels*/
> //hEdma1 = EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET);/* SPI-0 receive*/
> hEdma2 = EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET);/* SPI-0 transmit*/
> hEdma3 = EDMA_open(EDMA_CHA_REVT1, EDMA_OPEN_RESET);/*SPI-1 receive*/
> // hEdma4 = EDMA_open(EDMA_CHA_XEVT1, EDMA_OPEN_RESET);/*SPI-1 transmit*/
> #if 0
> hEdmadummy = EDMA_allocTable(-1); /* Dynamically allocates PaRAM RAM table*/
> EDMA_configArgs(hEdmadummy, /* Dummy or Terminating Table in PaRAM */
> 0x00000000, /* Terminate EDMA transfers by linking to */
> 0x00000000, /* this NULL table */
> 0x00000000,
> 0x00000000,
> 0x00000000,
> 0x00000000
> );
> #endif
> /* Enable sample rate generator GRST=1 */
> MCBSP_enableSrgr(hMcbsp0); /* Handle to SRGR */
> MCBSP_enableSrgr(hMcbsp1);
>
> #if (EDMA_SUPPORT) /* for EDMA supporting devices */
> EDMA_clearPram(0x00000000); /* Clear PaRAM RAM of the EDMA */
> set_interrupts_edma();
> #endif
>
> while(1)
> {
> int i = 0;
> xmit0_done=0;
> recv0_done=0;
> recv1_done=0;
> xmit1_done=0;
> LED1_on;
> //EDMA_link(hEdma2, hEdmadummy); /* Link terminating event to the EDMA event */
> // EDMA_link(hEdma3, hEdmadummy); /* Link terminating event to the EDMA event */
> /*enable SPI-1 Rx */
> EDMA_SPI_Rx(hMcbsp1,hEdma3, edmaInbuff1,xfer_size, McBSP1 );
> MCBSP_enableRcv(hMcbsp1);
> for(i=0;i<2;i++);
>
> /*enable SPI-0 Tx */
> EDMA_SPI_Tx(hMcbsp0,hEdma2, edmaOutbuff1,xfer_size,McBSP0 );
> /* enable Sample Rate genrator*/
> MCBSP_enableXmt(hMcbsp0);
> /* wait 2 cycles*/
> for(i=0;i<2;i++);
> while (!xmit0_done);
> //while (!recv1_done);
>
> /*reset EDMA Channels*/
> EDMA_reset(hEdma2);//Reset EDMA Tx Channel
> EDMA_reset(hEdma3);//Reset EDMA Rx Channel
>
> LED2_on ;
>
> }
>
> } /* end main */
>
> /*--------*/
> /* set_interrupts_edma() */
> /*--------*/
> void /* Set the interrupts */
> set_interrupts_edma(void) /* if the device supports EDMA */
> {
> IRQ_nmiEnable();
> IRQ_globalEnable();
> IRQ_reset(IRQ_EVT_EDMAINT);
> IRQ_disable(IRQ_EVT_EDMAINT);
> EDMA_intDisable(12); /* ch 12 for McBSP0 transmit event XEVT0 */
> EDMA_intDisable(13); /* ch 13 for McBSP0 receive event REVT0 */
> EDMA_intDisable(14); /* ch 14 for McBSP1 transmit event XEVT0 */
> EDMA_intDisable(15); /* ch 15 for McBSP1 receive event REVT0 */
> IRQ_clear(IRQ_EVT_EDMAINT);
> EDMA_intClear(12);
> EDMA_intClear(13);
> EDMA_intClear(14);
> EDMA_intClear(15);
>
> IRQ_enable(IRQ_EVT_EDMAINT);
> EDMA_intEnable(12);
> EDMA_intEnable(13);
> EDMA_intEnable(14);
> EDMA_intEnable(15);
> return;
> }
>
> void EDMA_SPI_Tx(MCBSP_Handle McBSPChannel,EDMA_Handle hEdmaChannel,\
> Uint32 *SourceAddress,Uint32 Count,Uint32 McBspNo)
> {
> volatile Uint32 unTemp;
> if(McBspNo ==1)
> {
> unTemp;
> }
> else
> {
> unTemp;
> }
> EDMA_clearPram(0x00000000);
> EDMA_configArgs(hEdmaChannel,
> #if(!C64_SUPPORT)
> EDMA_OPT_RMK(
> EDMA_OPT_PRI_LOW, /* High priority EDMA */
> EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits */
> EDMA_OPT_2DS_DEFAULT,
> EDMA_OPT_SUM_INC, /* Source increment by element size */
> EDMA_OPT_2DD_DEFAULT,
> EDMA_OPT_DUM_DEFAULT,
> EDMA_OPT_TCINT_YES, /* Enable Transfer Complete Interrupt */
> EDMA_OPT_TCC_OF(unTemp), /* TCCINT = 0xC, XEVT0 */
> EDMA_OPT_LINK_NO, /* Disable linking to NULL table */
> EDMA_OPT_FS_NO
> ),
> #endif
>
> EDMA_SRC_RMK((Uint32)SourceAddress), /*src to edmaOutbuff */
> EDMA_CNT_RMK(0,Count), /* set count equal to xfer_size */
> EDMA_DST_RMK(MCBSP_ADDRH(McBSPChannel, DXR)), /* dst addr to DXR0 */
> EDMA_IDX_RMK(0,0),
> EDMA_RLD_RMK(0,0)
> );
> #if 0
> hEdmadummy = EDMA_allocTable(-1); /* Dynamically allocates PaRAM RAM table*/
> EDMA_configArgs(hEdmadummy, /* Dummy or Terminating Table in PaRAM */
> 0x00000000, /* Terminate EDMA transfers by linking to */
> 0x00000000, /* this NULL table */
> 0x00000000,
> 0x00000000,
> 0x00000000,
> 0x00000000
> );
> #endif
> // EDMA_link(hEdma, hEdmadummy); /* Link terminating event to the EDMA event */
>
> /* Enable EDMA channels */
> EDMA_enableChannel(hEdmaChannel);
> }
> void EDMA_SPI_Rx(MCBSP_Handle McBSPChannel,EDMA_Handle hEdmaChannel,Uint32 *DestinationAddress,Uint32 Count,Uint32 McBspNo)
> {
> volatile Uint32 unTemp;
> if(McBspNo ==1)
> {
> unTemp; /* for configuring EDMA EVENT*/
> }
> else
> {
> unTemp;
> }
> //EDMA_clearPram(0x00000000);
> EDMA_configArgs(hEdmaChannel,
> #if (!C64_SUPPORT)
> EDMA_OPT_RMK(
> EDMA_OPT_PRI_HIGH, /* High priority EDMA */
> EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits */
> EDMA_OPT_2DS_DEFAULT,
> EDMA_OPT_SUM_DEFAULT,
> EDMA_OPT_2DD_DEFAULT,
> EDMA_OPT_DUM_INC, /* Destination increment by element size */
> EDMA_OPT_TCINT_YES, /* Enable Transfer Complete Interrupt */
> EDMA_OPT_TCC_OF(unTemp), /* TCCINT = 0xD, REVT0 */
> EDMA_OPT_LINK_YES, /* Enable linking to NULL table */
> EDMA_OPT_FS_NO
> ),
> #endif
> #if (C64_SUPPORT)
> EDMA_OPT_RMK(
> EDMA_OPT_PRI_HIGH, /* High priority EDMA */
> EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits */
> EDMA_OPT_2DS_DEFAULT,
> EDMA_OPT_SUM_DEFAULT,
> EDMA_OPT_2DD_DEFAULT,
> EDMA_OPT_DUM_INC, /* Destination increment by element size */
> EDMA_OPT_TCINT_YES, /* Enable Transfer Complete Interrupt */
> EDMA_OPT_TCC_OF(unTemp), /* TCCINT = 0xD, REVT0 */
> EDMA_OPT_TCCM_DEFAULT,
> EDMA_OPT_ATCINT_DEFAULT,
> EDMA_OPT_ATCC_DEFAULT,
> EDMA_OPT_PDTS_DEFAULT,
> EDMA_OPT_PDTD_DEFAULT,
> EDMA_OPT_LINK_NO, /* Enable linking to NULL table */
> EDMA_OPT_FS_NO
> ),
> #endif
> EDMA_SRC_RMK(MCBSP_ADDRH(McBSPChannel, DRR)), /*src to DRR1 */
> EDMA_CNT_RMK(0,Count), /*set count equal to xfer_size */
> EDMA_DST_RMK((Uint32)DestinationAddress), /* dst addr to edmaInbuff */
> EDMA_IDX_RMK(0,0),
> EDMA_RLD_RMK(0,0)
> );
> #if 0
> hEdmadummy = EDMA_allocTable(-1); /* Dynamically allocates PaRAM RAM table*/
> EDMA_configArgs(hEdmadummy, /* Dummy or Terminating Table in PaRAM */
> 0x00000000, /* Terminate EDMA transfers by linking to */
> 0x00000000, /* this NULL table */
> 0x00000000,
> 0x00000000,
> 0x00000000,
> 0x00000000
> );
> #endif
> // EDMA_link(hEdma, hEdmadummy); /* Link terminating event to the EDMA event */
>
> EDMA_enableChannel(hEdmaChannel); /* Enable EDMA channels */
> }
> /*--------*/
> /* DMA DATA TRANSFER COMPLETION ISRs */
> /*--------*/
> interrupt void /* vecs.asm hooks this up to IRQ 11 */
> c_int11(void) /* DMA ch2 */
> {
> xmit0_done = TRUE;
> return;
> }
> interrupt void /* vecs.asm hooks this up to IRQ 09 */
> c_int09(void) /* DMA ch1 */
> {
> recv0_done = TRUE;
> return;
> }
> interrupt void /* vecs.asm hooks this up to IRQ 08 */
> c_int08(void) /* for the EDMA */
> {
> #if (EDMA_SUPPORT)
> if (EDMA_intTest(12))
> {
> xmit0_done = TRUE;
> EDMA_intClear(12); /* clear CIPR bit so future interrupts can be recognized */
>
> }
> else if (EDMA_intTest( 13))
> {
> recv0_done = TRUE;
> EDMA_intClear(13); /* clear CIPR bit so future interrupts can be recognized */
> }
> else if (EDMA_intTest( 14))
> {
> xmit1_done = TRUE;
> EDMA_intClear(14); /* clear CIPR bit so future interrupts can be recognized */
> }
>
> else if (EDMA_intTest( 15))
> {
> recv1_done = TRUE;
> EDMA_intClear(15); /* clear CIPR bit so future interrupts can be recognized */
> }
> #endif
> return;
> }
> interrupt void
> c_int14(void)
> {
> //TimerEventHandler();
> asm (" nop; ");
> return;
> } /* end c_int14 */
>
> void init_emif(void )
> {
>
> /* EMIF setup */
> *(int *)EMIF_GCTL = 0x00000068;
> *(int *)EMIF_CE0 = 0xffffbf33; // CE0 SDRAM
> *(int *)EMIF_CE1 = 0x02208802; // CE1 Flash 8-bit
> *(int *)EMIF_CE2 = 0x22a28a22; // CE2 Daughtercard 32-bit async
> *(int *)EMIF_CE3 = 0x22a28a22; // CE3 Daughtercard 32-bit async
> if (Get_Board_Rev == 2)
> {
> *(int *)EMIF_SDRAMCTL = 0x57115000; // SDRAM control (16 Mb)
> }
> else
> {
> *(int *)EMIF_SDRAMCTL = 0x47115000; // SDRAM control (8 Mb)
> }
> *(int *)EMIF_SDRAMTIM = 0x00000578; // SDRAM timing (refresh)
> *(int *)EMIF_SDRAMEXT = 0x000a8529; // SDRAM Extension register
> }
>
> void init_cpld( void)
> {
> *(char*)CPLD_STAT = 0;
> *(char*)CPLD_DC = 0;
> *(char*)CPLD_MISC = 3; /* to enable Mcbsp -0,1*/
> }
> /**************************************end of file************************************************/
>
> /***********************mcbsp initializations**************************************************/
>
> /*--------*/
> /* init_mcbsp0_master() */
> /*--------*/
> /* MCBSP Config structure */
> /* Setup the MCBSP_0 as a master */
> void
> init_mcbsp0_master(void)
> {
> /
> MCBSP_Config mcbspCfg0 = {
> //0x00001000, /* spcr */ /*CLKSTPb*/
> 0x00001800, /*CLKSTPb*/
> 0x000100A0, /* rcr */
> 0x000100A0, /* xcr */
> 0x2000005f, /* srgr */ // 225/15= 15MHz
> 0x00000000, /* mcr */
> 0x00000000, /* rcer */
> 0x00000000, /* xcer */
> 0x00000A0C /* pcr */ /*CLKXP=1*/
> };
> hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);
> MCBSP_config(hMcbsp0, &mcbspCfg0);
>
> }
> /*--------*/
> /* init_mcbsp1_slave() */
> /*--------*/
> /* MCBSP Config structure */
> /* Setup the MCBSP_1 as a slave */
> void
> init_mcbsp1_slave(void)
> {
> MCBSP_Config mcbspCfg1 = {
> //0x00001000, /* spcr *//*CLKSTPb*/
> 0x00001800,
> 0x000000A0, /* rcr */
> 0x000000A0, /* xcr */
> 0x20000001, /* srgr */
> 0x00000000, /* mcr */
> 0x00000000, /* rcer */
> 0x00000000, /* xcer */
> 0x0000000C /* pcr */ /*CLKXP=1*/
> };
> hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
> MCBSP_config(hMcbsp1, &mcbspCfg1);
>
> }
>
> /********************************************************************************************/
>
> /*************************interrupt vector table******************************************/
> ********************************************************************************
> * Copyright (C) 2000 Texas Instruments Incorporated.
> * All Rights Reserved
> *------
> * FILENAME...... vecs.asm
> * DATE CREATED.. 12/06/2000
> * LAST MODIFIED. 12/06/2000
> ********************************************************************************
> *------
> * Global symbols defined here and exported out of this file
> *------
> .global _vectors
> .global _vector0
> .global _vector1
> .global _vector2
> .global _vector3
> .global _vector4
> .global _vector5
> .global _vector6
> .global _vector7
> .global _c_int08 ; Hookup the c_int08 ISR in main() for EDMA
> .global _c_int09 ; Hookup the c_int09 ISR in main() for DMA
> .global _vector10
> .global _c_int11 ; Hookup the c_int11 ISR in main() for DMA
> .global _vector12
> .global _vector13
> .global _c_int14 ; Hookup the c_int14 ISR in main()
> .global _vector15
> *------
> * Global symbols referenced in this file but defined somewhere else.
> * Remember that your interrupt service routines need to be referenced here.
> *------
> .ref _c_int00
> *------
> * This is a macro that instantiates one entry in the interrupt service table.
> *------
> VEC_ENTRY .macro addr
> STW B0,*--B15
> MVKL addr,B0
> MVKH addr,B0
> B B0
> LDW *B15++,B0
> NOP 2
> NOP
> NOP
> .endm
>
> *------
> * This is a dummy interrupt service routine used to initialize the IST.
> *------
> _vec_dummy:
> B B3
> NOP 5
> *------
> * This is the actual interrupt service table (IST). It is properly aligned and
> * is located in the subsection .text:vecs. This means if you don't explicitly
> * specify this section in your linker command file, it will default and link
> * into the .text section. Remember to set the ISTP register to point to this
> * table.
> *------
> .sect ".text:vecs"
> .align 1024
> _vectors:
> _vector0: VEC_ENTRY _vec_dummy
> _vector1: VEC_ENTRY _vec_dummy
> _vector2: VEC_ENTRY _vec_dummy
> _vector3: VEC_ENTRY _vec_dummy
> _vector4: VEC_ENTRY _vec_dummy
> _vector5: VEC_ENTRY _vec_dummy
> _vector6: VEC_ENTRY _vec_dummy
> _vector7: VEC_ENTRY _vec_dummy
> _vector8: VEC_ENTRY _c_int08 ; Hookup the c_int08 ISR in main() for EDMA
> _vector9: VEC_ENTRY _c_int09 ; Hookup the c_int09 ISR in main() for DMA
> _vector10: VEC_ENTRY _vec_dummy
> _vector11: VEC_ENTRY _c_int11 ; Hookup the c_int11 ISR in main() for DMA
> _vector12: VEC_ENTRY _vec_dummy
> _vector13: VEC_ENTRY _vec_dummy
> _vector14: VEC_ENTRY _c_int14 ; Hookup the c_int14 ISR in main()
> _vector15: VEC_ENTRY _vec_dummy
> *------
>
> ********************************************************************************
> * End of vecs.asm
> ********************************************************************************
>
> I am requesting to guide in this regard,
> Thanks
> SVS