About DM642 EDMA

Hi all.

I have a question to ask and hope someone could help me out.

The processor is DM642 600MHz;

I configure an 1D to 1D edma transfer from L2RAM to SDRAM,

the pertaining registers' configurations are as follows:

CCERL 0x0028BC00, EERL 0x03FFFFFF, ECRL 0x0028BC00,

after I started the transfer, the ESRL was 0x00200000, so channel 21 started transfer.

However, the register CIPRL didn't become 0x00200000, so the program always waited there.

I studied the documents about edma, but couldn't find out why.

The hardware configuration is of no problems. Start a New Thread

Hi,

it seems you have mixed-up two control registers: You have programmed
the CCERL register, which is used for EDMA chaining, instead of the CIERL
register - the channel interrupt enable register.

Regards,
A.Klemenz, D.SignT
At 10:15 19.12.2006 +0800, wrote:

>Hi all.
>
>I have a question to ask and hope someone could help me out.
>
>The processor is DM642 600MHz;
>
>I configure an 1D to 1D edma transfer from L2RAM to SDRAM,
>
>the pertaining registers' configurations are as follows:
>
>CCERL 0x0028BC00, EERL 0x03FFFFFF, ECRL 0x0028BC00,
>
>after I started the transfer, the ESRL was 0x00200000, so channel 21
>started transfer.
>
>However, the register CIPRL didn't become 0x00200000, so the program
>always waited there.
>
>I studied the documents about edma, but couldn't find out why.
>
>The hardware configuration is of no problems.
>
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Hi, Adolf
Thanks for your advice.
Yesterday, I examined the edma registers after edma configurations, i found that the CIPRL register for channel 3 was set to 1. But in the program, no transfer for this channel had been configured. The DM642 datasheet shows that channel 3 is for "EMIFA SDRAM timer interrupt", and the register EERL for this channel was set to 1. Later, i cleared the channel 3 bit in EERL and restarted the program, the edma transfer began,and pertaining bit in CIPRL was set.
I wonder, when emifa is used as interface for SDRAM, the edma channel 3 cannot be used for other edma transfer, is it right or not?
Thanks all.
Luo guangjun, Lemax Start a New Thread

Hi Lemax,

At 08:57 20.12.2006 +0800, =?gb2312?B?wt654r78?= wrote:

> I wonder, when emifa is used as interface for SDRAM, the edma channel 3
> cannot be used for other edma transfer, is it right or not?

Yes, this is true, also for other EDMA events: Channel 1 for example is
bound to Timer 0, and cannot be used for "general purpose" transfers if
this timer is in use.
The recommended method for unsynchronized memory-to-memory transfers is
using QDMA. The CSL contains suitable functions, e.g. DAT_copy() from
csl_dat.h.

Best Regards
A.Klemenz, D.SignT
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