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Performance of 16 or 32 bit data address on C6713

Started by z_11...@yahoo.com October 28, 2007
I have a TMS320C6713 (PYP), for communication with SDRAM, Does 32 or 16 bit data bus have undesired effect on performance of system? How can DMA or cache compensate it?
For a special software, dsp on DSK board has 70% cpu load, if I run same software on dsp (C6713 package PYP), how can I have same cpu load?

Regards,
Zahra
Zahra,

On 10/28/07, z...@yahoo.com wrote:
> I have a TMS320C6713 (PYP), for communication with SDRAM, Does 32 or 16 bit data bus have undesired effect on performance of system?

All 32 bit accesses to external memory will be slower.
- If your program loads a single 32 bit value, it will require 2
external memory accesses instead of 1.
- If you are executing code from external memory, the DSP must read 1
VLIW fetch packet. This will require 8 32 bit accesses with a 32 bit
bus. It will require 16 accesses with a 16 bit bus. This with have
the side effect of increasing the duty cycle ['busy time'] of the bus
and possibly having an additional 'slowing effect' on DMA.
> How can DMA or cache compensate it?
A well written application for a 32 bit bus will make the maximum use
of systems resources. Running with a 16 bit bus will only slow the
app down, unless all software runs in internal memory and I/O is 16
bits or less.
> For a special software, dsp on DSK board has 70% cpu load, if I run same software on dsp (C6713 package PYP), how can I have same cpu load?

You probably cannot. The issues are application and hardware dependent.
You can get an idea of where you are if you already have an app that
runs on the 6713 DSK. Run your app normally and check the load
[70%?]. Then modify the GEL file [or your app if it sets up the EMIF]
changing only the bus width from 32 to 16. Now measure the load again
[if the app still runs].

mikedunn
>
> Regards,
> Zahra
>
>