# clocks used in polyphase interpolation scheme

Started by July 18, 2008
```Greetings,

I am trying to understand how the clock domains work during
interpolation using the polyphase structure.

Does one use 2 different clocks during implementation(lets say an
interpolate by 2 FIR filter). One at the input and one at the output which
is 2x the input clock. IS this correct? or can you just use 1 clock
thru out, if the latter is true, how is this done?.

Chivak
```
```On Jul 18, 6:10 pm, "chivak" <cd_pra...@hotmail.com> wrote:
> Greetings,
>
>    I am trying to understand how the clock domains work during
>     interpolation using the polyphase structure.
>
>  Does one use 2 different clocks during implementation(lets say an
> interpolate by 2 FIR filter). One at the input and one at the output which
> is 2x the input clock. IS this correct? or can you just use 1 clock
>  thru out, if the latter is true, how is this done?.
>
>   Chivak

Assume you are using a memory for data storage (as opposed to a shift
register). Assume that the DSP which accesses the memory understands
how to set up a circular buffer.

1) New data arrives; write to memory location N
2) Form the first interpolated output by accessing location N, N-2,
N-4  ....... and multiply them by coefficients c0, c2, c4 ..... until
you run out of coefficients. Store in a register which is "double-
buffered". This calculation must be finished in less than 1/2 the
input sampling time, so that the 2nd register that follows the
register you just wrote to can "re-time" your output so it is
presented to the outside world at the proper time.
3) Form the 2nd interpolated output by accessing location N-1, N-3,
N-5  ....... and multiply them by coefficients c1, c3, c5 ..... until
you run out of coefficients. Store in the same register as before,
which once again gets re-timed by the register that follows it to the
2X clock rate.
4) N++ modulo LENGTH
5) wait for next input

Typically you must have a higher frequency clock anyway, to do the
calculations outlined above, so the input clock and the output clock
can all be derived from this common clock (in the real world this high-
frequency clock is likely generated by a PLL which locks onto a
multiple of the input clock rate, so you are a slave to the input
sampling clock rather than a master).

In theory you could code this so each output is "done" at exactly the
right time so the outputs would occur at exactly the right cycle, but
this is normally too much trouble, so you just calculate them, and
then use a hardware double-buffering scheme to get the output timing
correct.

If you are running at very fast clock rates then you may not be able
to order your calculation sequentially (you may need parallel
multipliers), in which case things are a bit different.