Xilinx FFT core's IFFT function not working? Dun Xilinx TEST their cores before releasing them?

Hi,
   has anybody used the FFT v4.1 core from Xilinx Core generator
before to do IFFT?
This is the scenario:
- I am using this config of the FFT core with the selected
configurations
   -pipelined, streaming
   -unscaled. input wave is 24 bits. output is 34 bits. coefficients
also 24 bits input

1) I use matlab to generate 24 bit complex waveform and save it into
text file
2) I run my testbench in modelsim (simulation). the testbench reads in
the text file of complex waveforms generated in (1). It is then fed
through the xilinx core generated FFT. This generates an FFT result.
(I have verified this output in matlab. It seems to be working fine.)

3) the FFT result is fed into another instantation of the same core.
this time, the core is configured to do IFFT by clearing the fwd_inv
signal (. Also, because the FFT core accepts a maximum input bus width
of 24 bits, I truncate the output from previous FFT from 34 bits to 24
bits before feeding into the IFFT core.
4) in theory, the normalised input and output waveform results should
be the same. I see some alarming results.

a) the output of the IFFT shows the first 7 samples of constant value.
This will result in some kind of phase shift. The output of the
simulation is piped into a text file. I read it into matlab and do my
analysis. In addition, viewing of the complex output waveform in
modelsim waveform viewer in analog step also confirms this. :(


Huh? Is that normal? Have i missed out something here? If not, isnt it
appalling? dun xilinx test their IP cores before releasing them?
Ridiculous right?


Chris

On Jul 24, 8:54 pm, chrisde...@gmail.com wrote:
> Hi,
>    has anybody used the FFT v4.1 core from Xilinx Core generator
> before to do IFFT?
> This is the scenario:
> - I am using this config of the FFT core with the selected
> configurations
>    -pipelined, streaming
>    -unscaled. input wave is 24 bits. output is 34 bits. coefficients
> also 24 bits input
>
> 1) I use matlab to generate 24 bit complex waveform and save it into
> text file
> 2) I run my testbench in modelsim (simulation). the testbench reads in
> the text file of complex waveforms generated in (1). It is then fed
> through the xilinx core generated FFT. This generates an FFT result.
> (I have verified this output in matlab. It seems to be working fine.)
>
> 3) the FFT result is fed into another instantation of the same core.
> this time, the core is configured to do IFFT by clearing the fwd_inv
> signal (. Also, because the FFT core accepts a maximum input bus width
> of 24 bits, I truncate the output from previous FFT from 34 bits to 24
> bits before feeding into the IFFT core.
> 4) in theory, the normalised input and output waveform results should
> be the same. I see some alarming results.
>
> a) the output of the IFFT shows the first 7 samples of constant value.
> This will result in some kind of phase shift. The output of the
> simulation is piped into a text file. I read it into matlab and do my
> analysis. In addition, viewing of the complex output waveform in
> modelsim waveform viewer in analog step also confirms this. :(
>
> Huh? Is that normal? Have i missed out something here? If not, isnt it
> appalling? dun xilinx test their IP cores before releasing them?
> Ridiculous right?
>
> Chris

To answer your questions:

1. No, that doesn't sound normal. While you might have some distortion
based upon the fixed-point calculations and truncation of the
intermediate FFT result, you should get something back that looks
pretty darn close to what you put in originally. Did you truncate the
signal correctly (that is, did you keep the right 24 bits?)?

2. I think Xilinx probably does test their cores before releasing
them. I'm sure you're not the first one to use it and do a similar
test. Have you contacted their support?

Jason