Bus width between registers in IIR

Hi all !

Thank you for reading this message !

I would like to know how width are the busses between the registers of an
IIR filter (ie implemented in a FPGA), because these filters have coeffs >
1. I have seen that the result of b0*x(n-1) can be as large as 5e5 with a
simple sin as input signal !

Could anybody help me ??

thanks in advance !

Sam

Sam (r�p. sans -no-sp-am) wrote:
> Hi all !
> 
> Thank you for reading this message !
> 
> I would like to know how width are the busses between the registers of an
> IIR filter (ie implemented in a FPGA), because these filters have coeffs >
> 1. I have seen that the result of b0*x(n-1) can be as large as 5e5 with a
> simple sin as input signal !
> 
> Could anybody help me ??
> 
> thanks in advance !
> 
> Sam

FPGA stands for field-programmable gate array. With one, you implement
whatever circuit you design (or choose). The number of bits in a design
is whatever the designer decides. In parallel designs, the width of the
busses is the bit count. In bit-serial designs, those numbers are
uncoupled. With proper scaling, the size of a number and the bit count
aren't necessarily related.

Jerry
-- 
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

Depends on your filter design.  Implementing an IIR filter in fixed point
usually has to use a rather wide word, and care needs to be taken in the
selection of the coefficients in order to avoid nasty quantization effects.
Implementation in an FPGA has little to do with the filter design other than
the physical realization of it.

"Sam (r�p. sans -no-sp-am)" wrote:

> Hi all !
>
> Thank you for reading this message !
>
> I would like to know how width are the busses between the registers of an
> IIR filter (ie implemented in a FPGA), because these filters have coeffs >
> 1. I have seen that the result of b0*x(n-1) can be as large as 5e5 with a
> simple sin as input signal !
>
> Could anybody help me ??
>
> thanks in advance !
>
> Sam

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

In the DSP chip world, different filter forms often yield "better" results in
terms of quantization, noise, magnitude of internal nodes, etc..  For example,
the 4-multiply normalized lattice/ladder IIR filter often gives excellent
results, though is more computationally intensive.  One chooses the appropriate
form for the job.  The same should hold true in FPGA implementations, though I
don't know if the various forms are commonly implemented, or if they usually
stick to Direct Form.  Maybe Ray can comment on that.  (I have no experience
with IIR filters in FPGAs, just in DSP chips.)

"Ray Andraka" <ray@andraka.com> wrote in message
news:4060D30A.E59702A1@andraka.com...
> Depends on your filter design.  Implementing an IIR filter in fixed point
> usually has to use a rather wide word, and care needs to be taken in the
> selection of the coefficients in order to avoid nasty quantization effects.
> Implementation in an FPGA has little to do with the filter design other than
> the physical realization of it.
>
> "Sam (r&#4294967295;p. sans -no-sp-am)" wrote:
>
> > Hi all !
> >
> > Thank you for reading this message !
> >
> > I would like to know how width are the busses between the registers of an
> > IIR filter (ie implemented in a FPGA), because these filters have coeffs >
> > 1. I have seen that the result of b0*x(n-1) can be as large as 5e5 with a
> > simple sin as input signal !
> >
> > Could anybody help me ??
> >
> > thanks in advance !
> >
> > Sam

Jerry Avins wrote:

(snip)

>> I would like to know how width are the busses between the 
 >> registers of an IIR filter (ie implemented in a FPGA),
 >> because these filters have coeffs > 1.
 >> I have seen that the result of b0*x(n-1) can be as large
>> as 5e5 with a simple sin as input signal !

(snip)

> FPGA stands for field-programmable gate array. With one, you implement
> whatever circuit you design (or choose). The number of bits in a design
> is whatever the designer decides. In parallel designs, the width of the
> busses is the bit count. In bit-serial designs, those numbers are
> uncoupled. With proper scaling, the size of a number and the bit count
> aren't necessarily related.

Most FPGA designs that I know of are parallel, though you can
choose the bit width often in units of 2, instead of 8 or 16
or 24, as on DSPs.

I believe it is usual to keep some extra bits for intermediate
values and truncate them later.  Exactly how many and how often
are implementation details.

-- glen

Ray Andraka wrote:

> Depends on your filter design.  Implementing an IIR filter in fixed point
> usually has to use a rather wide word, and care needs to be taken in the
> selection of the coefficients in order to avoid nasty quantization effects.
> Implementation in an FPGA has little to do with the filter design other than
> the physical realization of it.

(snip)

I was about to disagree with this, but then decided not to.

One difference is the size of the building blocks.  In a DSP you
have a small number of sized words you can operate on, usually
multiples of 8 or even 16.  Once you decide 16 isn't enough,
even for processing 16 bit data, you go to 24 or 32.
There is little difference between 17 and 24 bits.

Most FPGAs let you build ALU's in multiples of two bits.
Multipliers and look up tables are somewhat different though,
and may be quantized with other sizes.

The constraints are a little different, and some of that
difference is going to come out in the implementation.

-- glen

> > 1. I have seen that the result of b0*x(n-1) can be as large as 5e5 with
a
> > simple sin as input signal !

GRPWD!

FPGA arithmetic can be specified to the exact number of bits, not multiples of two
bits.  The difference with FPGAs is you don't need to carry around extra bits to
make the accumulator a multiple of some word size.  Still, that does not
practically affect the IIR filter design appreciably.  You have the same
quantization effects to worry about whether you use a microprocessor with fixed
point or an FPGA with fixed point.


>



--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Thank you for all these answers !

The only thing I would know is how many bits wide should I take for the
intermediate results when I use an IIR filter. The input data is 24 bit.
Should I use more than 24 bits to calculate the partial products, or not ?

Thank you !

Sam

Ray Andraka wrote:

> FPGA arithmetic can be specified to the exact number of bits,
 > not multiples of two bits.  The difference with FPGAs is you
 > don't need to carry around extra bits to make the accumulator
> a multiple of some word size.  Still, that does not
> practically affect the IIR filter design appreciably.  
 > You have the same quantization effects to worry about
 > whether you use a microprocessor with fixed
> point or an FPGA with fixed point.

Well, on a 16 bit processor the discussion goes something like:

"Is 16 bits enough, no, is 32 bits enough, yes."


In the FPGA case you have to ask about the cost and benefit
of each extra bit.  (I was considering 2 bit/CLB architectures,
but even there you don't need to use both.)  One possibility is
to choose an FPGA and then increase the bit width of intermediate
values until it doesn't fit.

-- glen