Hello all,
I have started to build a higher order (>1) Phase Lock Loop and it's
CLOSED LOOP transfer function I have determined as follows:
0.0312 z^-1 - 0.03119 z^-2
----------------------------------------
1 - 2.88 z^-1 + 2.791 z^-2 - 0.9113 z^-3
with Sampling time: 1.5 sec
How do I find the LOOP TIME CONSTANT for a higher order PLL (or, in
general to say, higher order closed loop system)?
Hope i have posted in the proper place. Any help or suggestion where to
find a guideline about this would be really appreciated.
Thank you all for your time,
Joydeep.
Time constant of a higer order closed loop system
Started by ●March 6, 2009
Reply by ●March 6, 20092009-03-06
joydeepdam wrote:> How do I find the LOOP TIME CONSTANT for a higher order PLL (or, in > general to say, higher order closed loop system)?Time constant is defined for the first order systems only. This is when the output changes by the factor of e. For the higher order systems, you have to define what do you mean by the time constant. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●March 6, 20092009-03-06
On Fri, 06 Mar 2009 08:09:57 -0600, Vladimir Vassilevsky wrote:> joydeepdam wrote: > > >> How do I find the LOOP TIME CONSTANT for a higher order PLL (or, in >> general to say, higher order closed loop system)? > > Time constant is defined for the first order systems only. This is when > the output changes by the factor of e. For the higher order systems, you > have to define what do you mean by the time constant. >The most valid use of the term "time constant" for higher order systems is if your higher order system has a dominant 1st-order pole -- then that pole's time constant can be stated as the system "time constant". Rise and settling times, overshoot and undershoot, are much more universal measures of a system's performance. -- http://www.wescottdesign.com
Reply by ●March 6, 20092009-03-06
On Mar 7, 2:04�am, "joydeepdam" <damjoyd...@googlemail.com> wrote:> Hello all, > I have started to build a higher order (>1) Phase Lock Loop and it's > CLOSED LOOP transfer function I have determined as follows: > > � � � �0.0312 z^-1 - 0.03119 z^-2 > ---------------------------------------- > 1 - 2.88 z^-1 + 2.791 z^-2 - 0.9113 z^-3 > > with Sampling time: 1.5 sec > > How do I find the LOOP TIME CONSTANT for a higher order PLL (or, in > general to say, higher order closed loop system)? > > Hope i �have posted in the proper place. Any help or suggestion where to > find a guideline about this would be really appreciated. > > Thank you all for your time, > Joydeep.You'll need Bode plots of the open loop system,phase margin etc. Design in analogue - convert to digital. Who the hell taught you control theory? Hardy
Reply by ●March 6, 20092009-03-06
HardySpicer wrote:> On Mar 7, 2:04 am, "joydeepdam" <damjoyd...@googlemail.com> wrote: >> Hello all, >> I have started to build a higher order (>1) Phase Lock Loop and it's >> CLOSED LOOP transfer function I have determined as follows: >> >> 0.0312 z^-1 - 0.03119 z^-2 >> ---------------------------------------- >> 1 - 2.88 z^-1 + 2.791 z^-2 - 0.9113 z^-3 >> >> with Sampling time: 1.5 sec >> >> How do I find the LOOP TIME CONSTANT for a higher order PLL (or, in >> general to say, higher order closed loop system)? >> >> Hope i have posted in the proper place. Any help or suggestion where to >> find a guideline about this would be really appreciated. >> >> Thank you all for your time, >> Joydeep. > > You'll need Bode plots of the open loop system,phase margin etc. > Design in analogue - convert to digital. > Who the hell taught you control theory? >Are you _criticizing_ "design in analog, convert to digital"? Or are you endorsing it? Analyze in analog, design in digital, don't forget that they're all approximations anyway. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●March 6, 20092009-03-06
On Mar 7, 2:07�pm, Tim Wescott <t...@seemywebsite.com> wrote:> HardySpicer wrote: > > On Mar 7, 2:04 am, "joydeepdam" <damjoyd...@googlemail.com> wrote: > >> Hello all, > >> I have started to build a higher order (>1) Phase Lock Loop and it's > >> CLOSED LOOP transfer function I have determined as follows: > > >> � � � �0.0312 z^-1 - 0.03119 z^-2 > >> ---------------------------------------- > >> 1 - 2.88 z^-1 + 2.791 z^-2 - 0.9113 z^-3 > > >> with Sampling time: 1.5 sec > > >> How do I find the LOOP TIME CONSTANT for a higher order PLL (or, in > >> general to say, higher order closed loop system)? > > >> Hope i �have posted in the proper place. Any help or suggestion where to > >> find a guideline about this would be really appreciated. > > >> Thank you all for your time, > >> Joydeep. > > > You'll need Bode plots of the open loop system,phase margin etc. > > Design in analogue - convert to digital. > > Who the hell taught you control theory? > > Are you _criticizing_ "design in analog, convert to digital"? �Or are > you endorsing it? > > Analyze in analog, design in digital, don't forget that they're all > approximations anyway. > > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" gives you just what it says. > See details athttp://www.wescottdesign.com/actfes/actfes.htmlDesign in analogue I am saying. Much faster. Some things it is better to do in digital but PLLs are not one of them. Hardy
Reply by ●March 7, 20092009-03-07
On Fri, 06 Mar 2009 19:09:29 -0800, HardySpicer wrote:> On Mar 7, 2:07 pm, Tim Wescott <t...@seemywebsite.com> wrote: >> HardySpicer wrote: >> > On Mar 7, 2:04 am, "joydeepdam" <damjoyd...@googlemail.com> wrote: >> >> Hello all, >> >> I have started to build a higher order (>1) Phase Lock Loop and it's >> >> CLOSED LOOP transfer function I have determined as follows: >> >> >> 0.0312 z^-1 - 0.03119 z^-2 >> >> ---------------------------------------- 1 - 2.88 z^-1 + 2.791 z^-2 >> >> - 0.9113 z^-3 >> >> >> with Sampling time: 1.5 sec >> >> >> How do I find the LOOP TIME CONSTANT for a higher order PLL (or, in >> >> general to say, higher order closed loop system)? >> >> >> Hope i have posted in the proper place. Any help or suggestion >> >> where to find a guideline about this would be really appreciated. >> >> >> Thank you all for your time, >> >> Joydeep. >> >> > You'll need Bode plots of the open loop system,phase margin etc. >> > Design in analogue - convert to digital. Who the hell taught you >> > control theory? >> >> Are you _criticizing_ "design in analog, convert to digital"? Or are >> you endorsing it? >> >> Analyze in analog, design in digital, don't forget that they're all >> approximations anyway. >> >> > Design in analogue I am saying. Much faster. Some things it is better to > do in digital but PLLs are not one of them. > > HardyI don't like the imprecision of taking a controller designed in the analog domain and converting to digital. And if you have nonlinearities in a controller your approximations break down a lot quicker with sampling rate. (And I often have occasion to implement PLLs entirely in the digital domain -- no going to analog at all). -- http://www.wescottdesign.com
Reply by ●March 7, 20092009-03-07
On Mar 8, 6:18�am, Tim Wescott <t...@seemywebsite.com> wrote:> On Fri, 06 Mar 2009 19:09:29 -0800, HardySpicer wrote: > > On Mar 7, 2:07�pm, Tim Wescott <t...@seemywebsite.com> wrote: > >> HardySpicer wrote: > >> > On Mar 7, 2:04 am, "joydeepdam" <damjoyd...@googlemail.com> wrote: > >> >> Hello all, > >> >> I have started to build a higher order (>1) Phase Lock Loop and it's > >> >> CLOSED LOOP transfer function I have determined as follows: > > >> >> � � � �0.0312 z^-1 - 0.03119 z^-2 > >> >> ---------------------------------------- 1 - 2.88 z^-1 + 2.791 z^-2 > >> >> - 0.9113 z^-3 > > >> >> with Sampling time: 1.5 sec > > >> >> How do I find the LOOP TIME CONSTANT for a higher order PLL (or, in > >> >> general to say, higher order closed loop system)? > > >> >> Hope i �have posted in the proper place. Any help or suggestion > >> >> where to find a guideline about this would be really appreciated. > > >> >> Thank you all for your time, > >> >> Joydeep. > > >> > You'll need Bode plots of the open loop system,phase margin etc. > >> > Design in analogue - convert to digital. Who the hell taught you > >> > control theory? > > >> Are you _criticizing_ "design in analog, convert to digital"? �Or are > >> you endorsing it? > > >> Analyze in analog, design in digital, don't forget that they're all > >> approximations anyway. > > > Design in analogue I am saying. Much faster. Some things it is better to > > do in digital but PLLs are not one of them. > > > Hardy > > I don't like the imprecision of taking a controller designed in the > analog domain and converting to digital. �And if you have nonlinearities > in a controller your approximations break down a lot quicker with > sampling rate. > > (And I often have occasion to implement PLLs entirely in the digital > domain -- no going to analog at all). > > --http://www.wescottdesign.comMaybe you can enlighten us all as to how this is done. For example, to design a PLL I need a Bode plot. I need to look at phase margin and add phase-lead-lag etc. Doing this in the digital domain is fraught with problems since there is no asmptotic approximations available for plotting frequency response. Of course you can use polynomials in z and simulations but that's more fiddling than real design. Hardy
Reply by ●March 7, 20092009-03-07
On Sat, 07 Mar 2009 11:42:47 -0800, HardySpicer wrote:> On Mar 8, 6:18 am, Tim Wescott <t...@seemywebsite.com> wrote: >> On Fri, 06 Mar 2009 19:09:29 -0800, HardySpicer wrote: >> > On Mar 7, 2:07 pm, Tim Wescott <t...@seemywebsite.com> wrote: >> >> HardySpicer wrote: >> >> > On Mar 7, 2:04 am, "joydeepdam" <damjoyd...@googlemail.com> wrote: >> >> >> Hello all, >> >> >> I have started to build a higher order (>1) Phase Lock Loop and >> >> >> it's CLOSED LOOP transfer function I have determined as follows: >> >> >> >> 0.0312 z^-1 - 0.03119 z^-2 >> >> >> ---------------------------------------- 1 - 2.88 z^-1 + 2.791 >> >> >> z^-2 - 0.9113 z^-3 >> >> >> >> with Sampling time: 1.5 sec >> >> >> >> How do I find the LOOP TIME CONSTANT for a higher order PLL (or, >> >> >> in general to say, higher order closed loop system)? >> >> >> >> Hope i have posted in the proper place. Any help or suggestion >> >> >> where to find a guideline about this would be really appreciated. >> >> >> >> Thank you all for your time, >> >> >> Joydeep. >> >> >> > You'll need Bode plots of the open loop system,phase margin etc. >> >> > Design in analogue - convert to digital. Who the hell taught you >> >> > control theory? >> >> >> Are you _criticizing_ "design in analog, convert to digital"? Or >> >> are you endorsing it? >> >> >> Analyze in analog, design in digital, don't forget that they're all >> >> approximations anyway. >> >> > Design in analogue I am saying. Much faster. Some things it is better >> > to do in digital but PLLs are not one of them. >> >> > Hardy >> >> I don't like the imprecision of taking a controller designed in the >> analog domain and converting to digital. And if you have >> nonlinearities in a controller your approximations break down a lot >> quicker with sampling rate. >> >> (And I often have occasion to implement PLLs entirely in the digital >> domain -- no going to analog at all). >> >> --http://www.wescottdesign.com > > Maybe you can enlighten us all as to how this is done. For example, to > design a PLL I need a Bode plot. > I need to look at phase margin and add phase-lead-lag etc. Doing this in > the digital domain is fraught with problems since there is no asmptotic > approximations available for plotting frequency response. Of course you > can use polynomials in z and simulations but that's more fiddling than > real design.I use a Bode plotter, typically Scilab*. I generally do the initial design using discrete-time state-space models or polynomials in z, if it's a SISO system I'll do Bode plot design. Then when the hardware is realized, I'll take frequency sweeps (in sampled-time), and do Bode plots again using the measured plant frequency response and the simulated controller transfer function. Finally I'll verify with open- and closed- loop Bode plots taken with the candidate final controller design. * Except that the Scilab team has undergone some very odd changes, and they've broken the 5.0.x build in a number of ways. So I'm currently sticking to the 4.1.2 build, and experimenting with the Scicoslab 4.1.3, which is a continuation of Scilab 4.1.2 made by approximately half of the Scilab team. Open source politics. Sigh. -- http://www.wescottdesign.com
Reply by ●March 10, 20092009-03-10
>On Sat, 07 Mar 2009 11:42:47 -0800, HardySpicer wrote: > >> On Mar 8, 6:18 am, Tim Wescott <t...@seemywebsite.com> wrote: >>> On Fri, 06 Mar 2009 19:09:29 -0800, HardySpicer wrote: >>> > On Mar 7, 2:07 pm, Tim Wescott <t...@seemywebsite.com> wrote: >>> >> HardySpicer wrote: >>> >> > On Mar 7, 2:04 am, "joydeepdam" <damjoyd...@googlemail.com>wrote:>>> >> >> Hello all, >>> >> >> I have started to build a higher order (>1) Phase Lock Loop and >>> >> >> it's CLOSED LOOP transfer function I have determined asfollows:>>> >>> >> >> 0.0312 z^-1 - 0.03119 z^-2 >>> >> >> ---------------------------------------- 1 - 2.88 z^-1 + 2.791 >>> >> >> z^-2 - 0.9113 z^-3 >>> >>> >> >> with Sampling time: 1.5 sec >>> >>> >> >> How do I find the LOOP TIME CONSTANT for a higher order PLL(or,>>> >> >> in general to say, higher order closed loop system)? >>> >>> >> >> Hope i have posted in the proper place. Any help orsuggestion>>> >> >> where to find a guideline about this would be reallyappreciated.>>> >>> >> >> Thank you all for your time, >>> >> >> Joydeep. >>> >>> >> > You'll need Bode plots of the open loop system,phase margin etc. >>> >> > Design in analogue - convert to digital. Who the hell taught you >>> >> > control theory? >>> >>> >> Are you _criticizing_ "design in analog, convert to digital"? Or >>> >> are you endorsing it? >>> >>> >> Analyze in analog, design in digital, don't forget that they'reall>>> >> approximations anyway. >>> >>> > Design in analogue I am saying. Much faster. Some things it isbetter>>> > to do in digital but PLLs are not one of them. >>> >>> > Hardy >>> >>> I don't like the imprecision of taking a controller designed in the >>> analog domain and converting to digital. And if you have >>> nonlinearities in a controller your approximations break down a lot >>> quicker with sampling rate. >>> >>> (And I often have occasion to implement PLLs entirely in the digital >>> domain -- no going to analog at all). >>> >>> --http://www.wescottdesign.com >> >> Maybe you can enlighten us all as to how this is done. For example, to >> design a PLL I need a Bode plot. >> I need to look at phase margin and add phase-lead-lag etc. Doing thisin>> the digital domain is fraught with problems since there is noasmptotic>> approximations available for plotting frequency response. Of courseyou>> can use polynomials in z and simulations but that's more fiddling than >> real design. > >I use a Bode plotter, typically Scilab*. I generally do the initial >design using discrete-time state-space models or polynomials in z, if >it's a SISO system I'll do Bode plot design. Then when the hardware is >realized, I'll take frequency sweeps (in sampled-time), and do Bode plots>again using the measured plant frequency response and the simulated >controller transfer function. Finally I'll verify with open- andclosed->loop Bode plots taken with the candidate final controller design. > >* Except that the Scilab team has undergone some very odd changes, and >they've broken the 5.0.x build in a number of ways. So I'm currently >sticking to the 4.1.2 build, and experimenting with the Scicoslab 4.1.3,>which is a continuation of Scilab 4.1.2 made by approximately half of the>Scilab team. > >Open source politics. Sigh. > >-- >http://www.wescottdesign.com >Hello all, Thank you
