FIFO controlled loop, PLL, FLL or something else?

I'm sure I'm not the first person to control an oscillator by the
amount of data in a FIFO, but I haven't found a reference to this
design which is similar to a PLL.

In place of a typical phase detector, I am using the count of samples
in the FIFO to control the DCO which drives the output clock.  Data is
clocked into the FIFO using the reference (input) clock.  I have an
integrator between the data count and the DCO phase step input.  The
data count is also offset so that it is zero when at the set point.

I am having trouble understanding how to model this design.  Is there
a unique name for this sort of circuit?  At first I was thinking it
was a frequency locked loop (FLL), but then I realized that the data
count works the same as a phase detector by integrating the difference
in frequency of the two signals, it just has a granularity of 1 cycle
and does not wrap around like typical phase detectors do.  So should I
be using the same model for this as I would use for a conventional PLL
using a standard phase detector?

I am having trouble getting the circuit to lock in quickly without
overshoot and hold lock as the frequency shifts.  I believe I need to
add a proportional element to the feedback loop.  I am also
considering using different coefficients when the loop is locked and
when not locked.

Am I making this hard and it just needs to be treated like any other
PLL?

Rick

On Mar 27, 11:04&#4294967295;am, rickman <gnu...@gmail.com> wrote:
> I'm sure I'm not the first person to control an oscillator by the
> amount of data in a FIFO, but I haven't found a reference to this
> design which is similar to a PLL.
>
> In place of a typical phase detector, I am using the count of samples
> in the FIFO to control the DCO which drives the output clock. &#4294967295;Data is
> clocked into the FIFO using the reference (input) clock. &#4294967295;I have an
> integrator between the data count and the DCO phase step input. &#4294967295;The
> data count is also offset so that it is zero when at the set point.
>
> I am having trouble understanding how to model this design. &#4294967295;Is there
> a unique name for this sort of circuit? &#4294967295;At first I was thinking it
> was a frequency locked loop (FLL), but then I realized that the data
> count works the same as a phase detector by integrating the difference
> in frequency of the two signals, it just has a granularity of 1 cycle
> and does not wrap around like typical phase detectors do. &#4294967295;So should I
> be using the same model for this as I would use for a conventional PLL
> using a standard phase detector?
>
> I am having trouble getting the circuit to lock in quickly without
> overshoot and hold lock as the frequency shifts. &#4294967295;I believe I need to
> add a proportional element to the feedback loop. &#4294967295;I am also
> considering using different coefficients when the loop is locked and
> when not locked.
>
> Am I making this hard and it just needs to be treated like any other
> PLL?
>
> Rick

I call it a "rate-locked loop", but I'm not sure there is an official
name. Other keywords include "elastic store" or "elastic buffer".

You can write loop equations and get response curves. If the buffer
length is B, the error is (x - B/2)/(B/2) where x is how much is in
the buffer. The feedback is through a standard lead-lag filter, the
output of which controls the buffer's empty rate.

John

On Mar 27, 11:04=A0am, rickman <gnu...@gmail.com> wrote:
> I'm sure I'm not the first person to control an oscillator by the
> amount of data in a FIFO, but I haven't found a reference to this
> design which is similar to a PLL.
>
> In place of a typical phase detector, I am using the count of samples
> in the FIFO to control the DCO which drives the output clock. =A0Data is
> clocked into the FIFO using the reference (input) clock. =A0I have an
> integrator between the data count and the DCO phase step input. =A0The
> data count is also offset so that it is zero when at the set point.
>
> I am having trouble understanding how to model this design. =A0Is there
> a unique name for this sort of circuit? =A0At first I was thinking it
> was a frequency locked loop (FLL), but then I realized that the data
> count works the same as a phase detector by integrating the difference
> in frequency of the two signals, it just has a granularity of 1 cycle
> and does not wrap around like typical phase detectors do. =A0So should I
> be using the same model for this as I would use for a conventional PLL
> using a standard phase detector?
>
> I am having trouble getting the circuit to lock in quickly without
> overshoot and hold lock as the frequency shifts. =A0I believe I need to
> add a proportional element to the feedback loop. =A0I am also
> considering using different coefficients when the loop is locked and
> when not locked.
>
> Am I making this hard and it just needs to be treated like any other
> PLL?
>
> Rick

I call it a "rate-locked loop", but I'm not sure there is an official
name. Other keywords include "elastic store" or "elastic buffer".

You can write loop equations and get response curves. If the buffer
length is B, the error is (x - B/2)/(B/2) where x is how much is in
the buffer. The feedback is through a standard lead-lag filter, the
output of which controls the buffer's empty rate.

John

On Mar 27, 11:04=A0am, rickman <gnu...@gmail.com> wrote:
> I'm sure I'm not the first person to control an oscillator by the
> amount of data in a FIFO, but I haven't found a reference to this
> design which is similar to a PLL.
>
> In place of a typical phase detector, I am using the count of samples
> in the FIFO to control the DCO which drives the output clock. =A0Data is
> clocked into the FIFO using the reference (input) clock. =A0I have an
> integrator between the data count and the DCO phase step input. =A0The
> data count is also offset so that it is zero when at the set point.
>
> I am having trouble understanding how to model this design. =A0Is there
> a unique name for this sort of circuit? =A0At first I was thinking it
> was a frequency locked loop (FLL), but then I realized that the data
> count works the same as a phase detector by integrating the difference
> in frequency of the two signals, it just has a granularity of 1 cycle
> and does not wrap around like typical phase detectors do. =A0So should I
> be using the same model for this as I would use for a conventional PLL
> using a standard phase detector?
>
> I am having trouble getting the circuit to lock in quickly without
> overshoot and hold lock as the frequency shifts. =A0I believe I need to
> add a proportional element to the feedback loop. =A0I am also
> considering using different coefficients when the loop is locked and
> when not locked.
>
> Am I making this hard and it just needs to be treated like any other
> PLL?
>
> Rick

I call it a "rate-locked loop", but I'm not sure there is an official
name. Other keywords include "elastic store" or "elastic buffer".

You can write loop equations and get response curves. If the buffer
length is B, the error is (x - B/2)/(B/2) where x is how much is in
the buffer. The feedback is through a standard lead-lag filter, the
output of which controls the buffer's empty rate.

John

rickman wrote:
> I'm sure I'm not the first person to control an oscillator by the
> amount of data in a FIFO, but I haven't found a reference to this
> design which is similar to a PLL.
> 
> In place of a typical phase detector, I am using the count of samples
> in the FIFO to control the DCO which drives the output clock.  Data is
> clocked into the FIFO using the reference (input) clock.  I have an
> integrator between the data count and the DCO phase step input.  The
> data count is also offset so that it is zero when at the set point.
> 
> I am having trouble understanding how to model this design.  Is there
> a unique name for this sort of circuit?

The name of this circuit is the toilet flush tank regulator. It was 
invented by Heron of Alexandria. Just go to the toilet and see how it works.

>  At first I was thinking it
> was a frequency locked loop (FLL), but then I realized that the data
> count works the same as a phase detector by integrating the difference
> in frequency of the two signals, it just has a granularity of 1 cycle
> and does not wrap around like typical phase detectors do.  So should I
> be using the same model for this as I would use for a conventional PLL
> using a standard phase detector?
> 
> I am having trouble getting the circuit to lock in quickly without
> overshoot and hold lock as the frequency shifts.  I believe I need to
> add a proportional element to the feedback loop.  I am also
> considering using different coefficients when the loop is locked and
> when not locked.
> 
> Am I making this hard and it just needs to be treated like any other
> PLL?

Keep it simple. If you don't want to pee, you don't have to force youself.



Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

> In place of a typical phase detector, I am using the count of samples
> in the FIFO to control the DCO which drives the output clock. �Data is
> clocked into the FIFO using the reference (input) clock. �I have an
> integrator between the data count and the DCO phase step input. �The
> data count is also offset so that it is zero when at the set point.
>
> I am having trouble understanding how to model this design. �Is there
> a unique name for this sort of circuit? �At first I was thinking it
> was a frequency locked loop (FLL), but then I realized that the data
> count works the same as a phase detector by integrating the difference
> in frequency of the two signals, it just has a granularity of 1 cycle
> and does not wrap around like typical phase detectors do. �So should I
> be using the same model for this as I would use for a conventional PLL
> using a standard phase detector?
>
> I am having trouble getting the circuit to lock in quickly without
> overshoot and hold lock as the frequency shifts. �I believe I need to
> add a proportional element to the feedback loop. �I am also
> considering using different coefficients when the loop is locked and
> when not locked.
>
> Am I making this hard and it just needs to be treated like any other
> PLL?

It's like a usual PLL but without the wraparound of the PD at 2pi.
There is no granularity of 1 Cycle, as long as the fill indicator is
not synchronized to any clock.

Add a proportional value in your loop, have a look at how you
synchronize the fill indicator.

On Fri, 27 Mar 2009 08:04:43 -0700 (PDT)
rickman <gnuarm@gmail.com> wrote:

> I'm sure I'm not the first person to control an oscillator by the
> amount of data in a FIFO, but I haven't found a reference to this
> design which is similar to a PLL.
> 
> In place of a typical phase detector, I am using the count of samples
> in the FIFO to control the DCO which drives the output clock.  Data is
> clocked into the FIFO using the reference (input) clock.  I have an
> integrator between the data count and the DCO phase step input.  The
> data count is also offset so that it is zero when at the set point.
> 
> I am having trouble understanding how to model this design.  Is there
> a unique name for this sort of circuit?  At first I was thinking it
> was a frequency locked loop (FLL), but then I realized that the data
> count works the same as a phase detector by integrating the difference
> in frequency of the two signals, it just has a granularity of 1 cycle
> and does not wrap around like typical phase detectors do.  So should I
> be using the same model for this as I would use for a conventional PLL
> using a standard phase detector?
> 
> I am having trouble getting the circuit to lock in quickly without
> overshoot and hold lock as the frequency shifts.  I believe I need to
> add a proportional element to the feedback loop.  I am also
> considering using different coefficients when the loop is locked and
> when not locked.
> 
> Am I making this hard and it just needs to be treated like any other
> PLL?
> 
> Rick

Sure sounds like it's just a phase detector.  That said, unless every
clock of the input clock is putting a sample into the FIFO you start
giving away gain pretty rapidly.  In a digital feedback loop,
gain=bits=ability to treat things as mathematically perfect rather than
mucking around in non-linear quantization effects.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

On Fri, 27 Mar 2009 08:19:43 -0700 (PDT), John <sampson164@gmail.com>
wrote:

>On Mar 27, 11:04&#4294967295;am, rickman <gnu...@gmail.com> wrote:
>> I'm sure I'm not the first person to control an oscillator by the
>> amount of data in a FIFO, but I haven't found a reference to this
>> design which is similar to a PLL.
>>
>> In place of a typical phase detector, I am using the count of samples
>> in the FIFO to control the DCO which drives the output clock. &#4294967295;Data is
>> clocked into the FIFO using the reference (input) clock. &#4294967295;I have an
>> integrator between the data count and the DCO phase step input. &#4294967295;The
>> data count is also offset so that it is zero when at the set point.
>>
>> I am having trouble understanding how to model this design. &#4294967295;Is there
>> a unique name for this sort of circuit? &#4294967295;At first I was thinking it
>> was a frequency locked loop (FLL), but then I realized that the data
>> count works the same as a phase detector by integrating the difference
>> in frequency of the two signals, it just has a granularity of 1 cycle
>> and does not wrap around like typical phase detectors do. &#4294967295;So should I
>> be using the same model for this as I would use for a conventional PLL
>> using a standard phase detector?
>>
>> I am having trouble getting the circuit to lock in quickly without
>> overshoot and hold lock as the frequency shifts. &#4294967295;I believe I need to
>> add a proportional element to the feedback loop. &#4294967295;I am also
>> considering using different coefficients when the loop is locked and
>> when not locked.
>>
>> Am I making this hard and it just needs to be treated like any other
>> PLL?
>>
>> Rick
>
>I call it a "rate-locked loop", but I'm not sure there is an official
>name. Other keywords include "elastic store" or "elastic buffer".
>
>You can write loop equations and get response curves. If the buffer
>length is B, the error is (x - B/2)/(B/2) where x is how much is in
>the buffer. The feedback is through a standard lead-lag filter, the
>output of which controls the buffer's empty rate.
>
>John

Also sometimes called a "delay-locked loop".

Eric Jacobsen
Minister of Algorithms
Abineau Communications
http://www.ericjacobsen.org

Blog: http://www.dsprelated.com/blogs-1/hf/Eric_Jacobsen.php

filter001@desinformation.de wrote:

> It's like a usual PLL but without the wraparound of the PD at 2pi.
> There is no granularity of 1 Cycle, as long as the fill indicator is
> not synchronized to any clock.
Hmmm, this comment makes me think this has all been hashed out under the 
topic of "Frequency locked loops".  Similar to a PLL, but there is no 
wraparound of the freq. detector.

Jon

On Mar 27, 1:25&#4294967295;pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
> On Fri, 27 Mar 2009 08:19:43 -0700 (PDT), John <sampson...@gmail.com>
> wrote:
>
>
>
> >On Mar 27, 11:04&#4294967295;am, rickman <gnu...@gmail.com> wrote:
> >> I'm sure I'm not the first person to control an oscillator by the
> >> amount of data in a FIFO, but I haven't found a reference to this
> >> design which is similar to a PLL.
>
> >> In place of a typical phase detector, I am using the count of samples
> >> in the FIFO to control the DCO which drives the output clock. &#4294967295;Data is
> >> clocked into the FIFO using the reference (input) clock. &#4294967295;I have an
> >> integrator between the data count and the DCO phase step input. &#4294967295;The
> >> data count is also offset so that it is zero when at the set point.
>
> >> I am having trouble understanding how to model this design. &#4294967295;Is there
> >> a unique name for this sort of circuit? &#4294967295;At first I was thinking it
> >> was a frequency locked loop (FLL), but then I realized that the data
> >> count works the same as a phase detector by integrating the difference
> >> in frequency of the two signals, it just has a granularity of 1 cycle
> >> and does not wrap around like typical phase detectors do. &#4294967295;So should I
> >> be using the same model for this as I would use for a conventional PLL
> >> using a standard phase detector?
>
> >> I am having trouble getting the circuit to lock in quickly without
> >> overshoot and hold lock as the frequency shifts. &#4294967295;I believe I need to
> >> add a proportional element to the feedback loop. &#4294967295;I am also
> >> considering using different coefficients when the loop is locked and
> >> when not locked.
>
> >> Am I making this hard and it just needs to be treated like any other
> >> PLL?
>
> >> Rick
>
> >I call it a "rate-locked loop", but I'm not sure there is an official
> >name. Other keywords include "elastic store" or "elastic buffer".
>
> >You can write loop equations and get response curves. If the buffer
> >length is B, the error is (x - B/2)/(B/2) where x is how much is in
> >the buffer. The feedback is through a standard lead-lag filter, the
> >output of which controls the buffer's empty rate.
>
> >John
>
> Also sometimes called a "delay-locked loop".

I am pretty sure that this is not a delay locked loop.  A DLL uses a
delay in the feedback path to generate an output that has a different
phase than the original.  This is often used to compensate for a delay
elsewhere in the clock path.

In one incarnation of the design of this circuit the error integrator
was enabled by the input clock enable.  If there was a phase shift in
the input and output clock enables, it would produce a single count of
difference during part of the cycle, but would be zero again by the
next input clock enable.  However, with the phase accumulator (DCO)
operating on each cycle of the main clock, this single count would be
added in producing what amounted to a fractional phase step compared
to the value in the error integrator.  The result is that the smallest
adjustments in output frequency would be made by the phasing of the
input and output signals.  However, the phase would never be corrected
in the error integrator.

This is a bit hard to describe in words.  I hope it is clear.

Rick