PLL based Clock

Would someone explain PLL based clock?

Phase locked loop

Thanks

justinvil1103 wrote:
> Would someone explain PLL based clock?
> 
> Phase locked loop
> 
That's like asking "would someone explain dirt?"

What part of the vast set of possibilities do you need to be informed of?

I would assume, hearing that phrase, that it's a clock line that's phase 
locked to some source for some reason.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

On Apr 21, 5:26&#4294967295;pm, "justinvil1103" <WillerJustin...@Bellsouth.net>
wrote:
> Would someone explain PLL based clock?
>
> Phase locked loop
>
> Thanks

In a processor, FPGA, or data acquisition card, a PLL can be used to
multiply an input clock up to a higher rate. The multiplication factor
is typically programmable. It's basically a synthesizer.

John

http://lmgtfy.com/?q=phase+locked+loop

"justinvil1103" <WillerJustinvil@Bellsouth.net> wrote in message 
news:XYSdnTMVddiKp3PUnZ2dnUVZ_tSdnZ2d@giganews.com...
> Would someone explain PLL based clock?
>
> Phase locked loop
>
> Thanks 

>http://lmgtfy.com/?q=phase+locked+loop
>

lol!!!! Nice one...

Chintan

>http://lmgtfy.com/?q=phase+locked+loop
>
>"justinvil1103" <WillerJustinvil@Bellsouth.net> wrote in message 
>news:XYSdnTMVddiKp3PUnZ2dnUVZ_tSdnZ2d@giganews.com...
>> Would someone explain PLL based clock?
>>
>> Phase locked loop
>>
>> Thanks 
>
>
>

That is a great link! That domain is definitely going in my back pocket
for  future use.