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Timing recovery design in PSK demodulation

Started by gobruins May 27, 2009
Hi, 
We are building a multichannel Q/8PSK demodulation system, we have
completed the carrier recovery design, and in the process of designing a
timing recovery loop to build a stable symbol clock. We have a coarse idea
how to do it, but would like to verify the feasibility.

The block diagram of our design is 

     187.5Msps        4R        4R                             
A/D  ----------> DDC ----> RRC ----> Fractional delayed filter --
                                 -->                            |
                               D |                              | 2R
                                 |---- control<---- Gardner   <--
                                       loop         Timing
                                                    Error Detector

The A/D output data rate is 187.5MSPS.
DDC is the digital down converter used for channelization. 
R is symbol rate, which is 19.2KHz in our design.
RRC is root raised cosine filter used for matched filtering
D is the delay feed back to the fractional delayed filter(FD).

Once the loop is stable we should be able to have the symbol sampled at
the peak at the FD filter output.

Here are some details that we are not very sure about our design.

1. RRC input data rate. we choose 4 times symbol rate because the in band
magnitude response of a 5 order FD filter is within 0.01dB. So we get less
magnitude distortion. We might also can use 8R instead of 4R. Higher than
8R will be hard to design a DDC with good channel rejection performance. Is
this the right way to decide the data rate? Is there any other issues that
need to be considered?

2. D range of the FD filter. If we use 4R at FD filter input, then every
period we have 4 samples, which means the symbol timing offset can be any
number within [-2,+2]. So the FD filter has to precisely generate the
waveform of x(t-D) where D=[-2,+2]. Is my understanding correct at this
point? If this is correct, if we use 8R at FD filter input, then the input
range of D becomes [-4,+4], does the FD filter work for this range of D
input? 
   This is the part that I am confused. I saw some reference saying the FD
filter works with D in [0~1]. If this is true, how do I deal with a timing
error that is say 1.5?

3. Gardner timing error detector. I know this method works good for
sequences with lots of transitions like 10101010101. If I am sampling right
at the end point and mid point of each symbol, I get 0 at TED output. But
when consecutive 1's and 0's appear like 110100101000, the TED output is
distorted, even I sample right on spot, my TED output is not zero. The
symbol clock adjusted itself according to this 'error'. So what we see as
last will be a jitter on the symbol clock. This seems to be embedded error
for this method. How should I avoid this problem? We are thinking of adding
a moving average component to smooth this error, will that work?

Thanks.

gobruins wrote:

> Hi, > We are building a multichannel Q/8PSK demodulation system,
Oh, come on. Judging on the stilted phrases, abbreviations and the utter cluelessness, you are building a stupident homework, right?
> 1. RRC input data rate. we choose 4 times symbol rate because the in band > magnitude response of a 5 order FD filter is within 0.01dB. So we get less > magnitude distortion. We might also can use 8R instead of 4R. Higher than > 8R will be hard to design a DDC with good channel rejection performance. Is > this the right way to decide the data rate? Is there any other issues that > need to be considered?
Two samples per symbol is all that needed for demodulation.
> 2. D range of the FD filter. If we use 4R at FD filter input, then every > period we have 4 samples, which means the symbol timing offset can be any > number within [-2,+2]. So the FD filter has to precisely generate the > waveform of x(t-D) where D=[-2,+2]. Is my understanding correct at this > point? If this is correct, if we use 8R at FD filter input, then the input > range of D becomes [-4,+4], does the FD filter work for this range of D > input? This is the part that I am confused.
I am confused also. No idea what are you driving here.
> 3. Gardner timing error detector. I know this method works good for > sequences with lots of transitions like 10101010101.
Any timing error detector works on transitions.
> If I am sampling right > at the end point and mid point of each symbol, I get 0 at TED output. But > when consecutive 1's and 0's appear like 110100101000, the TED output is > distorted, even I sample right on spot, my TED output is not zero. The > symbol clock adjusted itself according to this 'error'. So what we see as > last will be a jitter on the symbol clock. This seems to be embedded error > for this method. How should I avoid this problem? We are thinking of adding > a moving average component to smooth this error, will that work?
Any non-data aided timing detector has the data related noise. The simple way to deal with that is a lot of averaging (~hundreds of symbols). The smart way is correct the symbol sync for the data pattern, i.e. making the detector data aided. Moving average in the feedback loop is not a good idea, a minimum phase filter would be better solution. VLV
>Hi, >We are building a multichannel Q/8PSK demodulation system, we have >completed the carrier recovery design, and in the process of designing a >timing recovery loop to build a stable symbol clock. We have a coarse
idea
>how to do it, but would like to verify the feasibility. > >The block diagram of our design is > > 187.5Msps 4R 4R >A/D ----------> DDC ----> RRC ----> Fractional delayed filter -- > --> | > D | | 2R > |---- control<---- Gardner <-- > loop Timing > Error Detector > >The A/D output data rate is 187.5MSPS. >DDC is the digital down converter used for channelization. >R is symbol rate, which is 19.2KHz in our design. >RRC is root raised cosine filter used for matched filtering >D is the delay feed back to the fractional delayed filter(FD). > >Once the loop is stable we should be able to have the symbol sampled at >the peak at the FD filter output. > >Here are some details that we are not very sure about our design. > >1. RRC input data rate. we choose 4 times symbol rate because the in
band
>magnitude response of a 5 order FD filter is within 0.01dB. So we get
less
>magnitude distortion. We might also can use 8R instead of 4R. Higher
than
>8R will be hard to design a DDC with good channel rejection performance.
Is
>this the right way to decide the data rate? Is there any other issues
that
>need to be considered? > >2. D range of the FD filter. If we use 4R at FD filter input, then every >period we have 4 samples, which means the symbol timing offset can be
any
>number within [-2,+2]. So the FD filter has to precisely generate the >waveform of x(t-D) where D=[-2,+2]. Is my understanding correct at this >point? If this is correct, if we use 8R at FD filter input, then the
input
>range of D becomes [-4,+4], does the FD filter work for this range of D >input? > This is the part that I am confused. I saw some reference saying the
FD
>filter works with D in [0~1]. If this is true, how do I deal with a
timing
>error that is say 1.5? >
According to MATLAB demo "Timing Recovery using Fixed-Rate Resampling", you need a NCO to generate a symbol clock and fractional delay filter "u" input is from 0 to 1. There is a timing control unit and is anyone can explain the actual function of this unit? B.
> > >gobruins wrote: > >> Hi, >> We are building a multichannel Q/8PSK demodulation system, > >Oh, come on. Judging on the stilted phrases, abbreviations and the utter
>cluelessness, you are building a stupident homework, right? > >> 1. RRC input data rate. we choose 4 times symbol rate because the in
band
>> magnitude response of a 5 order FD filter is within 0.01dB. So we get
less
>> magnitude distortion. We might also can use 8R instead of 4R. Higher
than
>> 8R will be hard to design a DDC with good channel rejection
performance. Is
>> this the right way to decide the data rate? Is there any other issues
that
>> need to be considered? > >Two samples per symbol is all that needed for demodulation.
One sample per symbol is all that is needed for demodulation. Two is a more common number to use as it avoids various problems.
>> 2. D range of the FD filter. If we use 4R at FD filter input, then
every
>> period we have 4 samples, which means the symbol timing offset can be
any
>> number within [-2,+2]. So the FD filter has to precisely generate the >> waveform of x(t-D) where D=[-2,+2]. Is my understanding correct at
this
>> point? If this is correct, if we use 8R at FD filter input, then the
input
>> range of D becomes [-4,+4], does the FD filter work for this range of
D
>> input? This is the part that I am confused. > >I am confused also. No idea what are you driving here.
Typically books talk about a fractional symbol delay, working over the range 0 to 1 symbol times. I think the OP has confused samples with symbols.
>> 3. Gardner timing error detector. I know this method works good for >> sequences with lots of transitions like 10101010101. > >Any timing error detector works on transitions. > >> If I am sampling right >> at the end point and mid point of each symbol, I get 0 at TED output.
But
>> when consecutive 1's and 0's appear like 110100101000, the TED output
is
>> distorted, even I sample right on spot, my TED output is not zero. The >> symbol clock adjusted itself according to this 'error'. So what we see
as
>> last will be a jitter on the symbol clock. This seems to be embedded
error
>> for this method. How should I avoid this problem? We are thinking of
adding
>> a moving average component to smooth this error, will that work? > >Any non-data aided timing detector has the data related noise. The >simple way to deal with that is a lot of averaging (~hundreds of >symbols). The smart way is correct the symbol sync for the data pattern,
>i.e. making the detector data aided. Moving average in the feedback loop
>is not a good idea, a minimum phase filter would be better solution.
Data aided symbol sync usually requires training data. Non-data aided methods, like Gardner, work blind. We don't know the kind of signal the OP is trying to demodulate. Any timing detector will only work well with heavy filtering. Even if the detector can hit the spot symbol by symbol for a perfect clean signal, it will only stabilise on a real world noisy signal with filtering. Most timing detectors are based on the assumption that the data source is reasonably white. If it is, then Gardner will settle on 8PSK with fairly light damping, as long as the excess bandwidth is not too limited (say
>20%), and will even settle reasonably well using small QAM constellations
when using heavier damping. Steve
On May 28, 3:32&#2013266080;pm, "billykao" <billy....@gmail.com> wrote:
> >Hi, > >We are building a multichannel Q/8PSK demodulation system, we have > >completed the carrier recovery design, and in the process of designing a > >timing recovery loop to build a stable symbol clock. We have a coarse > idea > >how to do it, but would like to verify the feasibility. > > >The block diagram of our design is > > > &#2013266080; &#2013266080; 187.5Msps &#2013266080; &#2013266080; &#2013266080; &#2013266080;4R &#2013266080; &#2013266080; &#2013266080; &#2013266080;4R &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; > >A/D &#2013266080;----------> DDC ----> RRC ----> Fractional delayed filter -- > > &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; --> &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080;| > > &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; D | &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080;| 2R > > &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; |---- control<---- Gardner &#2013266080; <-- > > &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; loop &#2013266080; &#2013266080; &#2013266080; &#2013266080; Timing > > &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080;Error Detector > > >The A/D output data rate is 187.5MSPS. > >DDC is the digital down converter used for channelization. > >R is symbol rate, which is 19.2KHz in our design. > >RRC is root raised cosine filter used for matched filtering > >D is the delay feed back to the fractional delayed filter(FD). > > >Once the loop is stable we should be able to have the symbol sampled at > >the peak at the FD filter output. > > >Here are some details that we are not very sure about our design. > > >1. RRC input data rate. we choose 4 times symbol rate because the in > band > >magnitude response of a 5 order FD filter is within 0.01dB. So we get > less > >magnitude distortion. We might also can use 8R instead of 4R. Higher > than > >8R will be hard to design a DDC with good channel rejection performance. > Is > >this the right way to decide the data rate? Is there any other issues > that > >need to be considered? > > >2. D range of the FD filter. If we use 4R at FD filter input, then every > >period we have 4 samples, which means the symbol timing offset can be > any > >number within [-2,+2]. So the FD filter has to precisely generate the > >waveform of x(t-D) where D=[-2,+2]. Is my understanding correct at this > >point? If this is correct, if we use 8R at FD filter input, then the > input > >range of D becomes [-4,+4], does the FD filter work for this range of D > >input? > > &#2013266080; This is the part that I am confused. I saw some reference saying the > FD > >filter works with D in [0~1]. If this is true, how do I deal with a > timing > >error that is say 1.5? > > According to MATLAB demo "Timing Recovery using Fixed-Rate Resampling", > you need a NCO to generate a symbol clock and fractional delay filter "u" > input is from 0 to 1. &#2013266080;There is a timing control unit and is anyone can > explain the actual function of this unit? > > B.
Why don't you open the demo and see what's inside? Principally there are only few "correct" ways of doing synchronization, but there are gazillions of ways that different people encapsulate the functions, and gazillions of ways to call each of the sub-blocks.

steveu wrote:

> Data aided symbol sync usually requires training data.
Training data is required if the channel is unknown and bad enough so you can't pull yourself out without a trainer.
> Non-data aided > methods, like Gardner, work blind.
The result of Gardner can be corrected according to the received data pattern. At the least, the influence of the transmit/receive pulse shaping can be accounted for.
> We don't know the kind of signal the OP > is trying to demodulate.
Probably double precision float. :-)
> Any timing detector will only work well with heavy filtering.
This is actually one of the problems I had to work on recently. Heavy filtering -> slow asqusition and narrow locking range.
> Even if the > detector can hit the spot symbol by symbol for a perfect clean signal, it > will only stabilise on a real world noisy signal with filtering. Most > timing detectors are based on the assumption that the data source is > reasonably white. If it is, then Gardner will settle on 8PSK with fairly > light damping, as long as the excess bandwidth is not too limited (say >>20%), and will even settle reasonably well using small QAM constellations > when using heavier damping.
The merit of Gardner detector is the simplicity; however one can do a lot better with the data aided methods. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com