On Fri, 29 May 2009 15:15:38 -0700, rickman wrote:> I posted a message a couple of months ago on a PLL I am working on, but > I can't continue that thread. The circuit is using a PLL to generate an > output clock which is a integer ratio multiple of the input clock. The > purpose is to pull data out of a FIFO at the same rate it is going in > and to keep a fixed amount of data in the FIFO while driving the output > which is an interleave circuit. So the output clock needs to be N/(N-1) > times the input clock and the PLL must maintain a zero phase > relationship (long term) between the input clock and the divided down > output clock in order to keep amount of data in the FIFO constant. > > The circuit I came up with for this uses an up/down counter as the phase > comparator. The the leading edge of the input clock makes it count up > and the leading edge of the feedback clock makes it count down. If both > occur during a given system clock cycle, the count is held as it is when > there are no leading edges. > > From what I have seen, this is considered a bang-bang phase comparator > in the analog world.I haven't seen the phrase "bang-bang" applied to a phase comparator. At any rate, if your loop bandwidth is significantly less than your clock rate the phase comparator reading will average out. Are you using the count as your phase measurement, or just the last bit, or what? If your goal is to maintain a nice FIFO fill level, why not use the FIFO fill level as your phase comparator?> I guess it works the same in the digital world > too. The filter I am using is an integrator added to a proportional > (each with gain factors) to produce the step size fed to the NCO. The > NCO produces a clock enable on overflow which feeds the interleave > circuit. The interleave circuit returns N-1 out of every N clocks to > pull data out of the FIFO and feedback to the PLL. > > I simulated this with gain settings of A=64 for the proportional path > and B=1/128 for the integrator output. I also tried other values and > they are all stable, but some settle faster and others ring more before > settling. I picked the values that seem to give me quick settling and > track an input frequency change well without a lot of oscillation. > > All that said, when I do an analysis of the filter using the z- > transform, I get a pole on the unit circle at 1,0 and a zero very close > to it at 0.999...,0. It would appear that the zero is stabilizing the > pole and frequencies other than very near DC. But a DC input is > stabilized by the overall loop. The question is, how do I include the > rest of the loop in a z-transform analysis? Or is this not the right > way to approach it?That is the right way to approach it. You need to model the behavior of the phase comparator and the DCO in such a way that you can make z-domain models of them. Then you can just put the loop together and see how it looks. If you take the input to the DCO to be the desired frequency (or phase increment, or target count), and the output to be the phase (or timing) offset, then the DCO will act like an integrator -- so you can treat it as having an action k_o / (z - 1). Finding k_o will be interesting, in no small part because it depends on how you define your inputs and outputs. Your best bet will be to fit the behavior to an integrator with a gain of the right dimensions, then figure out the value of the integrator gain. Some DCO arrangements will be nonlinear. Specifically, if you use a simple count-to-value-and-reset, or load-value-and-reload-at-zero, then the frequency will be the reciprocal of the command. You'll have to linearize this by taking the derivative of the frequency with respect to the command at the nominal rate. Ask here if that's the case... Ditto with your phase comparator. It will respond to the phase of the DCO with a linear relationship, so you can model it as a simple gain (call it k_phi). Once you have those two models, then you can model your whole loop. This loop model will look an awful lot like loop models for analog PLLs, so you could do a lot worse than to search around the web for basic PLL discussions. I'd suggest a book such as http://www.powells.com/ partner/30696/biblio/0136627439, except that it is entirely oriented toward analog PLLs, so you only want it if you feel confident in translating everything to digital. If I haven't lost enough shame to suggest it already, you may also want a copy of my book: http://www.wescottdesign.com/actfes/actfes.html. It doesn't go into PLLs specifically, but it certainly gives you some strong background in control theory. -- http://www.wescottdesign.com
All Digital PLL Design
Started by ●May 29, 2009
Reply by ●May 30, 20092009-05-30
Reply by ●May 31, 20092009-05-31
On May 30, 12:40�pm, Tim Wescott <t...@seemywebsite.com> wrote:> On Fri, 29 May 2009 15:15:38 -0700, rickman wrote: > > I posted a message a couple of months ago on a PLL I am working on, but > > I can't continue that thread. �The circuit is using a PLL to generate an > > output clock which is a integer ratio multiple of the input clock. �The > > purpose is to pull data out of a FIFO at the same rate it is going in > > and to keep a fixed amount of data in the FIFO while driving the output > > which is an interleave circuit. �So the output clock needs to be N/(N-1) > > times the input clock and the PLL must maintain a zero phase > > relationship (long term) between the input clock and the divided down > > output clock in order to keep amount of data in the FIFO constant. > > > The circuit I came up with for this uses an up/down counter as the phase > > comparator. The the leading edge of the input clock makes it count up > > and the leading edge of the feedback clock makes it count down. �If both > > occur during a given system clock cycle, the count is held as it is when > > there are no leading edges. > > > From what I have seen, this is considered a bang-bang phase comparator > > in the analog world. > > I haven't seen the phrase "bang-bang" applied to a phase comparator. �At > any rate, if your loop bandwidth is significantly less than your clock > rate the phase comparator reading will average out. �Are you using the > count as your phase measurement, or just the last bit, or what? > > If your goal is to maintain a nice FIFO fill level, why not use the FIFO > fill level as your phase comparator?BINGO! You win the cupie doll! That *is* what I am using, the fifo fill counter offset so that it is zero at the proper fill level. The idea is that by using an integrator in the filter section, the error term will return to zero and the FIFO level will be restored. The entire count is used, but in my simulations I only saw the value range less than 100 +- and I think it was much less depending on the coefficients on the proportional and integrator terms.> > I guess it works the same in the digital world > > too. �The filter I am using is an integrator added to a proportional > > (each with gain factors) to produce the step size fed to the NCO. �The > > NCO produces a clock enable on overflow which feeds the interleave > > circuit. �The interleave circuit returns N-1 out of every N clocks to > > pull data out of the FIFO and feedback to the PLL. > > > I simulated this with gain settings of A=64 for the proportional path > > and B=1/128 for the integrator output. �I also tried other values and > > they are all stable, but some settle faster and others ring more before > > settling. �I picked the values that seem to give me quick settling and > > track an input frequency change well without a lot of oscillation. > > > All that said, when I do an analysis of the filter using the z- > > transform, I get a pole on the unit circle at 1,0 and a zero very close > > to it at 0.999...,0. �It would appear that the zero is stabilizing the > > pole and frequencies other than very near DC. �But a DC input is > > stabilized by the overall loop. �The question is, how do I include the > > rest of the loop in a z-transform analysis? �Or is this not the right > > way to approach it? > > That is the right way to approach it. �You need to model the behavior of > the phase comparator and the DCO in such a way that you can make z-domain > models of them. �Then you can just put the loop together and see how it > looks. > > If you take the input to the DCO to be the desired frequency (or phase > increment, or target count), and the output to be the phase (or timing) > offset, then the DCO will act like an integrator -- so you can treat it > as having an action k_o / (z - 1). �Finding k_o will be interesting, in > no small part because it depends on how you define your inputs and > outputs. �Your best bet will be to fit the behavior to an integrator with > a gain of the right dimensions, then figure out the value of the > integrator gain. > > Some DCO arrangements will be nonlinear. �Specifically, if you use a > simple count-to-value-and-reset, or load-value-and-reload-at-zero, then > the frequency will be the reciprocal of the command. �You'll have to > linearize this by taking the derivative of the frequency with respect to > the command at the nominal rate. �Ask here if that's the case...I'm not sure what you mean in this paragraph. The DCO is just an accumulator. The output of the filter is the step size, or as you say, the frequency. This is repeatedly added to the value in the accumulator and when it rolls over, the carry out is used as a clock enable which is the clock output. The filter output is *NOT* being used as the max value in a counter. That would invert the sense and as you say, make it non-linear.> Ditto with your phase comparator. �It will respond to the phase of the > DCO with a linear relationship, so you can model it as a simple gain > (call it k_phi).Yes, I get that now. Although it has a delay, so there is a z term associated with it.> Once you have those two models, then you can model your whole loop. �This > loop model will look an awful lot like loop models for analog PLLs, so > you could do a lot worse than to search around the web for basic PLL > discussions. �I'd suggest a book such ashttp://www.powells.com/ > partner/30696/biblio/0136627439, except that it is entirely oriented > toward analog PLLs, so you only want it if you feel confident in > translating everything to digital. > > If I haven't lost enough shame to suggest it already, you may also want a > copy of my book: �http://www.wescottdesign.com/actfes/actfes.html. �It > doesn't go into PLLs specifically, but it certainly gives you some strong > background in control theory. > > --http://www.wescottdesign.comThanks, I tried to order the book using a discount code and it didn't apply the code after it said the discount would be applied at checkout. I wrote them. If they can get this fixed, I will order the book. Rick
