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DDS - PLL hybrid linear sweep synthesizer

Started by Paul Wolf July 13, 2009
Dear professionals, 

I am interested in designing of a DDS / PLL hybrid linear sweep
synthesizer. I would like to buy a DDS and PLL from Analog Devices. In my
case the DDS would be able to produce a highly linear frequency chirp from
0 to 400 MHz, but I have to produce an RF chirp of the frequency up to 4
GHz. So I have found the concept of generating the chirp by the DDS and
multiplying its frequency by a consecutively connected PLL. In this case
the DDS acts as a reference source. I would be happy to get any ideas about
solving the following problems: 

- What components can You recommend to me? 
- How should I design the loop filter? 
- What aspects should I take into account for correct designing of the
hybrid system? 
- How can I simulate the hybrid system? 
- Will it be a (rolling?) locked/ settled PLL? 

Maybe You can provide a list of literature I should read. 

Thank You very much, Paul


On Jul 13, 11:07&#4294967295;pm, "Paul Wolf" <kstatni...@gmail.com> wrote:
> Dear professionals, > > I am interested in designing of a DDS / PLL hybrid linear sweep > synthesizer. I would like to buy a DDS and PLL from Analog Devices. In my > case the DDS would be able to produce a highly linear frequency chirp from > 0 to 400 MHz, but I have to produce an RF chirp of the frequency up to 4 > GHz. So I have found the concept of generating the chirp by the DDS and > multiplying its frequency by a consecutively connected PLL. In this case > the DDS acts as a reference source. I would be happy to get any ideas about > solving the following problems: > > - What components can You recommend to me? > - How should I design the loop filter? > - What aspects should I take into account for correct designing of the > hybrid system? > - How can I simulate the hybrid system? > - Will it be a (rolling?) locked/ settled PLL? > > Maybe You can provide a list of literature I should read. > > Thank You very much, Paul
If all you require is a sweep what's wrong with just feeding a sawtooth waveform into the VCO of the PLL, and not locking it at all? Using PLLs as multipliers multiplies the noise too. If you want things really clean and quiet it may not be the best strategy. Steve
steveu@dis.org wrote:
> On Jul 13, 11:07 pm, "Paul Wolf" <kstatni...@gmail.com> wrote: >> Dear professionals, >> >> I am interested in designing of a DDS / PLL hybrid linear sweep >> synthesizer. I would like to buy a DDS and PLL from Analog Devices. In my >> case the DDS would be able to produce a highly linear frequency chirp from >> 0 to 400 MHz, but I have to produce an RF chirp of the frequency up to 4 >> GHz. So I have found the concept of generating the chirp by the DDS and >> multiplying its frequency by a consecutively connected PLL. In this case >> the DDS acts as a reference source. I would be happy to get any ideas about >> solving the following problems: >> >> - What components can You recommend to me? >> - How should I design the loop filter? >> - What aspects should I take into account for correct designing of the >> hybrid system? >> - How can I simulate the hybrid system? >> - Will it be a (rolling?) locked/ settled PLL? >> >> Maybe You can provide a list of literature I should read. >> >> Thank You very much, Paul > > If all you require is a sweep what's wrong with just feeding a > sawtooth waveform into the VCO of the PLL, and not locking it at all? > Using PLLs as multipliers multiplies the noise too. If you want things > really clean and quiet it may not be the best strategy.
Now why didn't I think of that?! Jerry -- Engineering is the art of making what you want from things you can get. &#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;

Paul Wolf wrote:
> Dear professionals, > > I am interested in designing of a DDS / PLL hybrid linear sweep > synthesizer. I would like to buy a DDS and PLL from Analog Devices. In my > case the DDS would be able to produce a highly linear frequency chirp from > 0 to 400 MHz, but I have to produce an RF chirp of the frequency up to 4 > GHz. So I have found the concept of generating the chirp by the DDS and > multiplying its frequency by a consecutively connected PLL. In this case > the DDS acts as a reference source.
Start with the definition of the parameters and the requirements to the accuracy of the synthesised signal. Everything else depends on that.
> I would be happy to get any ideas about > solving the following problems:
> - What components can You recommend to me?
The components that are available from Digikey or Mouser.
> - How should I design the loop filter?
The main design tools are the clever head and the stubborn arse.
> - What aspects should I take into account for correct designing of the > hybrid system?
Time and money, as usual.
> - How can I simulate the hybrid system?
Writing a program in C for simulation is a matter of an hour.
> - Will it be a (rolling?) locked/ settled PLL?
Eh? Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
> > >Paul Wolf wrote: >> Dear professionals, >> >> I am interested in designing of a DDS / PLL hybrid linear sweep >> synthesizer. I would like to buy a DDS and PLL from Analog Devices. In
my
>> case the DDS would be able to produce a highly linear frequency chirp
from
>> 0 to 400 MHz, but I have to produce an RF chirp of the frequency up to
4
>> GHz. So I have found the concept of generating the chirp by the DDS
and
>> multiplying its frequency by a consecutively connected PLL. In this
case
>> the DDS acts as a reference source. > >Start with the definition of the parameters and the requirements to the >accuracy of the synthesised signal. Everything else depends on that. >
Dear Vladimir, I have to produce a highly linear frequency chirp. Therefore I take the approach described above. I would take an Integer-N-PLL with appropriate max RF frequency input. The comparison frequency would be in the order of 40-50 MHz. So, the chirp signal will go from 40 to 50 MHz in 1 millisecond. My main question is how to design the loop filter. Should it be narrow or wide?
>> I would be happy to get any ideas about >> solving the following problems: > >> - What components can You recommend to me? > >The components that are available from Digikey or Mouser. >
I would like to take them from Analog Devices.
>> - How should I design the loop filter? > >The main design tools are the clever head and the stubborn arse.
Can You give me a set of formulas or math relationships to calculate the transfer function of the loop filter and of the whole chirp synthesizer?
>> - What aspects should I take into account for correct designing of the >> hybrid system? > >Time and money, as usual. > >> - How can I simulate the hybrid system? > >Writing a program in C for simulation is a matter of an hour. >
Do You have any examples? I would like to do it in Simulink. What do You think about it?
>> - Will it be a (rolling?) locked/ settled PLL? > >Eh? >
I think that at the start of chirp the PLL will lock to the starting frequency and then will "follow" the changing "crystal" frequency (chirp). So, will it be a completely settled mode?
> >Vladimir Vassilevsky >DSP and Mixed Signal Design Consultant >http://www.abvolt.com >

Paul Wolf wrote:
>> > I have to produce a highly linear frequency chirp.
How linear is "highly linear" ? What are the requirements to the spurious/out of band products? It could be difficult to satisfy the spectral purity and the accuracy requirements at the same time.
> Therefore I take the > approach described above. I would take an Integer-N-PLL with appropriate > max RF frequency input. The comparison frequency would be in the order of > 40-50 MHz. So, the chirp signal will go from 40 to 50 MHz in 1 millisecond. > My main question is how to design the loop filter. Should it be narrow or > wide?
You need a PLL with the double integration for the accurate tracking of the linear frequency sweep. You may also need a feedforward control of the VCO to reduce the initial transient error.
> Can You give me a set of formulas or math relationships to calculate the > transfer function of the loop filter and of the whole chirp synthesizer?
I would recommend the classic book: F. Gardner "Phaselock Techiques" Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Paul Wolf wrote:

   ...

> I have to produce a highly linear frequency chirp. Therefore I take the > approach described above. I would take an Integer-N-PLL with appropriate > max RF frequency input. The comparison frequency would be in the order of > 40-50 MHz. So, the chirp signal will go from 40 to 50 MHz in 1 millisecond.
That's a sweep rate GHz/sec. I suggest that you calculate the width of the sidebands that will be produced.
> My main question is how to design the loop filter. Should it be narrow or > wide?
Define narrow and wide.
>>> I would be happy to get any ideas about >>> solving the following problems: >>> - What components can You recommend to me? >> The components that are available from Digikey or Mouser. >> > I would like to take them from Analog Devices. >>> - How should I design the loop filter? >> The main design tools are the clever head and the stubborn arse. > Can You give me a set of formulas or math relationships to calculate the > transfer function of the loop filter and of the whole chirp synthesizer? >>> - What aspects should I take into account for correct designing of the >>> hybrid system? >> Time and money, as usual. >> >>> - How can I simulate the hybrid system? >> Writing a program in C for simulation is a matter of an hour. >> > Do You have any examples? I would like to do it in Simulink. What do You > think about it? >>> - Will it be a (rolling?) locked/ settled PLL? >> Eh? >> > I think that at the start of chirp the PLL will lock to the starting > frequency and then will "follow" the changing "crystal" frequency (chirp).
At a sweep of 10 GHz/sec, how closely do you expect it to follow?
> So, will it be a completely settled mode?
Completely settled? The question should probably be "how unsettled"? Jerry -- Engineering is the art of making what you want from things you can get. &#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#4294967295;