when i compiling my code on CCS v 2.2 and target device is DM642 this feedback information is coming in asm file can anybody help me in decoding what does epilog prolog means and for a good pipelined code it should be less or not ? or any other changes required ? ;*----------------------------------------------------------------------------* ;* SOFTWARE PIPELINE INFORMATION ;* ;* Loop source line : 528 ;* Loop opening brace source line : 528 ;* Loop closing brace source line : 542 ;* Known Minimum Trip Count : 4 ;* Known Maximum Trip Count : 4 ;* Known Max Trip Count Factor : 4 ;* Loop Carried Dependency Bound(^) : 0 ;* Unpartitioned Resource Bound : 10 ;* Partitioned Resource Bound(*) : 10 ;* Resource Partition: ;* A-side B-side ;* .L units 0 0 ;* .S units 1 0 ;* .D units 10* 10* ;* .M units 0 0 ;* .X cross paths 0 0 ;* .T address paths 10* 10* ;* Long read paths 0 0 ;* Long write paths 0 0 ;* Logical ops (.LS) 0 0 (.L or .S unit) ;* Addition ops (.LSD) 6 6 (.L or .S or .D unit) ;* Bound(.L .S .LS) 1 0 ;* Bound(.L .S .D .LS .LSD) 6 6 ;* ;* Searching for software pipeline schedule at ... ;* ii = 10 Schedule found with 2 iterations in parallel ;* ;* Register Usage Table: ;* +-----------------------------------------------------------------+ ;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB| ;* |00000000001111111111222222222233|00000000001111111111222222222233| ;* |01234567890123456789012345678901|01234567890123456789012345678901| ;* |--------------------------------+--------------------------------| ;* 0: |** * ***** * | ** * | ;* 1: |** * ***** * | **** | ;* 2: |** * ***** * | ** ** | ;* 3: |** * ***** * | ***** | ;* 4: |** * **** * | *** * | ;* 5: |** * **** * | **** | ;* 6: |** * ** * * | **** | ;* 7: |** **** * | **** | ;* 8: |** * **** * | **** | ;* 9: |** * ***** * | **** | ;* +-----------------------------------------------------------------+ ;* ;* Done ;* ;* Epilog not removed ;* Collapsed epilog stages : 0 ;* Collapsed prolog stages : 1 ;* Minimum required memory pad : 0 bytes ;* ;* Minimum safe trip count : 1 ;*----------------------------------------------------------------------------*
epilog and prolog
Started by ●March 12, 2004
Reply by ●March 16, 20042004-03-16
Ankur: Prolog means cycles spent prior to the loop "getting ready" for the loop, and Epilog means cycles spent after the loop "cleaning up". For example, in a typical DSP implementation (w/ multifunction instructions) of an FIR, 1)SUM=0; 2)C=m(x); D=m(y); 3)loop (loop only N-1 times)->{SUM+=C*D; C=m(x+n); D=m(y+n);} 4)SUM+=C*D; C=coeff, D=data. 2) would be the loop prolog, 3) is the loop, and 4) is the loop epilog. I don't think 1) is usually considered part of the prolog, as prolog and epilog are usuallay only the parts of the "loop" that are "unwrapped" for speed of execution. Jim "ankur" <ankur10011@yahoo.co.in> wrote in message news:9926292f.0403112110.462e390@posting.google.com...> when i compiling my code on CCS v 2.2 and target device is DM642 this > feedback information is coming in asm file can anybody help me in > decoding what does epilog prolog means and for a good pipelined code > it should be less or not ? > > or any other changes required ? > > > > >;*-------------------------------------------------------------------------- --*> ;* SOFTWARE PIPELINE INFORMATION > ;* > ;* Loop source line : 528 > ;* Loop opening brace source line : 528 > ;* Loop closing brace source line : 542 > ;* Known Minimum Trip Count : 4 > ;* Known Maximum Trip Count : 4 > ;* Known Max Trip Count Factor : 4 > ;* Loop Carried Dependency Bound(^) : 0 > ;* Unpartitioned Resource Bound : 10 > ;* Partitioned Resource Bound(*) : 10 > ;* Resource Partition: > ;* A-side B-side > ;* .L units 0 0 > ;* .S units 1 0 > ;* .D units 10* 10* > ;* .M units 0 0 > ;* .X cross paths 0 0 > ;* .T address paths 10* 10* > ;* Long read paths 0 0 > ;* Long write paths 0 0 > ;* Logical ops (.LS) 0 0 (.L or .S unit) > ;* Addition ops (.LSD) 6 6 (.L or .S or .D > unit) > ;* Bound(.L .S .LS) 1 0 > ;* Bound(.L .S .D .LS .LSD) 6 6 > ;* > ;* Searching for software pipeline schedule at ... > ;* ii = 10 Schedule found with 2 iterations in parallel > ;* > ;* Register Usage Table: > ;*+-----------------------------------------------------------------+> ;*|AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|> ;*|00000000001111111111222222222233|00000000001111111111222222222233|> ;*|01234567890123456789012345678901|01234567890123456789012345678901|> ;*|--------------------------------+--------------------------------|> ;* 0: |** * ***** * | ** * > | > ;* 1: |** * ***** * | **** > | > ;* 2: |** * ***** * | ** ** > | > ;* 3: |** * ***** * | ***** > | > ;* 4: |** * **** * | *** * > | > ;* 5: |** * **** * | **** > | > ;* 6: |** * ** * * | **** > | > ;* 7: |** **** * | **** > | > ;* 8: |** * **** * | **** > | > ;* 9: |** * ***** * | **** > | > ;*+-----------------------------------------------------------------+> ;* > ;* Done > ;* > ;* Epilog not removed > ;* Collapsed epilog stages : 0 > ;* Collapsed prolog stages : 1 > ;* Minimum required memory pad : 0 bytes > ;* > ;* Minimum safe trip count : 1 >;*-------------------------------------------------------------------------- --*