Dear all,
I am encountering a problem to write AD1881A registers. I had
posted this before. I could able to read the codec registers; but
unable to write to it. I tried to communicate the codec at AC'97 mode.
I am copying my earlier post at the end for your easy reference.
We tried the CODEC in slot-16 mode, at this mode the codec is working
fine.
At the application note (Interfacing the ADSP-21065L SHARC DSP to the
AD1819A AC'97 Sound Port Codec
-http://www.analog.com/UploadedFiles/Application_Notes/250806129AD1819A_21065L.pdf
), the AD was mentioned that; it is needed to write successively to
Serial Configuration register(0x74) for changing the CODEC from AC97
to slot16 mode. So I tried successively write some other value (0x1000
� not enabling the slot 16 mode) to this register; and it was
successful (I read back). So it was possible to write to the serial
configuration register at AC97 mode. But still then i was not able
write any other register at AC'97 mode. In another attempt I tried
successive write to the Volume Control Register to 0x0000 (just after
the codec � DSP link established; the same method as the serial
configuration register writing). But it was not successful.
Is any problem for working the Codec at AC'97 mode while connected to
a SHARC processor? What are the use of MODE pin and the CS0 and CS1
pins (I found very little information about these pins)? Please give
me some direction to solve this problem. Thanks in advance.
regards
ajith
Previous Post:
I am working on a custom designed board with ADSP 21065L and AD1881A
(AC'97 rev 2.1 complaint) CODEC. The interface is same as the
AD1819-21065L interface provided by Analog Devices. The CODEC
generates the BIT_CLK and in return DSP generates the SYNC. I probed
these things by using CRO. I am facing a problem while writing to the
CODEC registers. I am able to read the CODEC registers, but I am
unable to write to the registers. i have done a CODEC initialization
on another board in which ADSP 21065L processor is connected to the
TLV320AIC27 CODEC. In this case i could read and write to the CODEC
registers. Give some hints for possible causes. Does this AD1881 needs
some specific register initialization before it starts initializing
AC97 specific registers? I am specifically asking about the serial
configuration registers and the miscellaneous control bit registers.
Please note that I wish to work AD1881A in AC97 mode; not in slot16
mode.
Set one register and then read back, and then sets another one; is
this sequence works? What is the Codec register write latency?
CS0, CS1 and MODE pin are left floated in our design. Is it has any
effects on CODEC initialization? In AD1881 data sheet these pins are
left unconnected, and there is only little information for these pins.
But in AD1819 Codec, it is mentioned that CS0 and CS1 are tied to HIGH
for single Codec application.
Does any layout issues or power supply cause this kind of problems
(Consistently able to read from the registers and unable to write on
it. I checked the power down control status register; it shows that
all the 4 subsections are ready)?
Is anybody experiences similar problem? Please give me some hints for
solve this problem. Thanks.
Unable to Write AD1881A registers
Started by ●March 9, 2004
Reply by ●March 9, 20042004-03-09
ajith_pc@yahoo.com (Ajith Kumar P C) wrote in news:18eae751.0403090920.12008c83@posting.google.com:> Dear all, > I am encountering a problem to write AD1881A registers. I had > posted this before. I could able to read the codec registers; but > unable to write to it. I tried to communicate the codec at AC'97 mode. > I am copying my earlier post at the end for your easy reference. > > We tried the CODEC in slot-16 mode, at this mode the codec is working > fine. > > At the application note (Interfacing the ADSP-21065L SHARC DSP to the > AD1819A AC'97 Sound Port Codec > -http://www.analog.com/UploadedFiles/Application_Notes/250806129AD1819A > _21065L.pdf ), the AD was mentioned that; it is needed to write > successively to Serial Configuration register(0x74) for changing the > CODEC from AC97 to slot16 mode. So I tried successively write some > other value (0x1000 � not enabling the slot 16 mode) to this register; > and it was successful (I read back). So it was possible to write to > the serial configuration register at AC97 mode. But still then i was > not able write any other register at AC'97 mode. In another attempt I > tried successive write to the Volume Control Register to 0x0000 (just > after the codec � DSP link established; the same method as the serial > configuration register writing). But it was not successful. > > Is any problem for working the Codec at AC'97 mode while connected to > a SHARC processor? What are the use of MODE pin and the CS0 and CS1 > pins (I found very little information about these pins)? Please give > me some direction to solve this problem. Thanks in advance. > > regards > ajith >I have written too many drivers for AC-97 codecs including the AD1881A. They all work in standard AC-97 (not slot 16 mode). I don't have any specific suggestion to solving your problem but I have found the following procedures helpful: 1. Download the AC-97 specification. This is often more clear than the AD1881A datasheet for standard register use. 2. Make sure you have pulldowns on SDATA_OUT (DT) & SYNC (FS). 3. Look at the interface with a logic analyzer or DSO. I have solved many device driver problems with codecs using this method. 4. Look at other AC-97 devices. This may give you a better understanding of generic AC-97 usage. I have also found that in a few cases, what works on one AC-97 doesn't work on all others. For example, make sure you actually fill the unused time slot data in your transmit buffer with 0s. 5. ID0 & ID1 select whether the AC-97 is a master or slave. Best to tie these pins high (assuming only one AC-97) Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com> Previous Post: > > I am working on a custom designed board with ADSP 21065L and > AD1881A > (AC'97 rev 2.1 complaint) CODEC. The interface is same as the > AD1819-21065L interface provided by Analog Devices. The CODEC > generates the BIT_CLK and in return DSP generates the SYNC. I probed > these things by using CRO. I am facing a problem while writing to the > CODEC registers. I am able to read the CODEC registers, but I am > unable to write to the registers. i have done a CODEC initialization > on another board in which ADSP 21065L processor is connected to the > TLV320AIC27 CODEC. In this case i could read and write to the CODEC > registers. Give some hints for possible causes. Does this AD1881 needs > some specific register initialization before it starts initializing > AC97 specific registers? I am specifically asking about the serial > configuration registers and the miscellaneous control bit registers. > Please note that I wish to work AD1881A in AC97 mode; not in slot16 > mode. > Set one register and then read back, and then sets another one; is > this sequence works? What is the Codec register write latency? > CS0, CS1 and MODE pin are left floated in our design. Is it has any > effects on CODEC initialization? In AD1881 data sheet these pins are > left unconnected, and there is only little information for these pins. > But in AD1819 Codec, it is mentioned that CS0 and CS1 are tied to HIGH > for single Codec application. > Does any layout issues or power supply cause this kind of problems > (Consistently able to read from the registers and unable to write on > it. I checked the power down control status register; it shows that > all the 4 subsections are ready)? > Is anybody experiences similar problem? Please give me some hints for > solve this problem. Thanks. >-- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
Reply by ●March 10, 20042004-03-10
Dear Clark,
Thanks for your direction. My problem is that I am able to
read Codec registers and was unable to write these registers in AC'97
mode. In AC'97 mode; by using repeated write command just after the
Codec-DSP link is established, i am able to write the Serial
Configuration register. But the same procedure failed if i use some
other register other than the Serial Configuration Register (i tried
with the Master Volume register (0x02)). Today I tried a single write
to Serial Configuration register after all the sub sections are ready;
it works fine. My explanation for your directions are in line with
your directions.
> 1. Download the AC-97 specification. This is often more clear than the
> AD1881A datasheet for standard register use.
>
yes. I downloaded the material from Intel site.
> 2. Make sure you have pulldowns on SDATA_OUT (DT) & SYNC (FS).
>
The SDATA_OUT line is pulled down. But the Sync line not pulled down.
The Sync shows a low value before enabling the Serial port and the
Codec.
> 3. Look at the interface with a logic analyzer or DSO. I have solved many
> device driver problems with codecs using this method.
>
> 4. Look at other AC-97 devices. This may give you a better understanding
> of generic AC-97 usage. I have also found that in a few cases, what works
> on one AC-97 doesn't work on all others. For example, make sure you
> actually fill the unused time slot data in your transmit buffer with 0s.
>
yes. The unused slot bits are filled with zeros.
> 5. ID0 & ID1 select whether the AC-97 is a master or slave. Best to tie
> these pins high (assuming only one AC-97)
>
I am not quite sure about ID0 and ID1. Are you asking to tie the CS0
and CS1 pins to HIGH? The CS0 and CS1 and MODE pins of the AD1881A are
left unconnected. We are using only one Codec interfaced with
ADSP21065L.
regards
ajith
> > Dear all,
> > I am encountering a problem to write AD1881A registers. I had
> > posted this before. I could able to read the codec registers; but
> > unable to write to it. I tried to communicate the codec at AC'97 mode.
> > I am copying my earlier post at the end for your easy reference.
> >
> > We tried the CODEC in slot-16 mode, at this mode the codec is working
> > fine.
> >
> > At the application note (Interfacing the ADSP-21065L SHARC DSP to the
> > AD1819A AC'97 Sound Port Codec
> > -http://www.analog.com/UploadedFiles/Application_Notes/250806129AD1819A
> > _21065L.pdf ), the AD was mentioned that; it is needed to write
> > successively to Serial Configuration register(0x74) for changing the
> > CODEC from AC97 to slot16 mode. So I tried successively write some
> > other value (0x1000 ? not enabling the slot 16 mode) to this register;
> > and it was successful (I read back). So it was possible to write to
> > the serial configuration register at AC97 mode. But still then i was
> > not able write any other register at AC'97 mode. In another attempt I
> > tried successive write to the Volume Control Register to 0x0000 (just
> > after the codec ? DSP link established; the same method as the serial
> > configuration register writing). But it was not successful.
> >
> > Is any problem for working the Codec at AC'97 mode while connected to
> > a SHARC processor? What are the use of MODE pin and the CS0 and CS1
> > pins (I found very little information about these pins)? Please give
> > me some direction to solve this problem. Thanks in advance.
> >
> > regards
> > ajith
> >
>
> I have written too many drivers for AC-97 codecs including the AD1881A.
> They all work in standard AC-97 (not slot 16 mode).
>
> I don't have any specific suggestion to solving your problem but I have
> found the following procedures helpful:
>
> 1. Download the AC-97 specification. This is often more clear than the
> AD1881A datasheet for standard register use.
>
> 2. Make sure you have pulldowns on SDATA_OUT (DT) & SYNC (FS).
>
> 3. Look at the interface with a logic analyzer or DSO. I have solved many
> device driver problems with codecs using this method.
>
> 4. Look at other AC-97 devices. This may give you a better understanding
> of generic AC-97 usage. I have also found that in a few cases, what works
> on one AC-97 doesn't work on all others. For example, make sure you
> actually fill the unused time slot data in your transmit buffer with 0s.
>
> 5. ID0 & ID1 select whether the AC-97 is a master or slave. Best to tie
> these pins high (assuming only one AC-97)
>
> Al Clark
> Danville Signal Processing, Inc.
> --------------------------------------------------------------------
> Purveyors of Fine DSP Hardware and other Cool Stuff
> Available at http://www.danvillesignal.com
>
>
>
>
> > Previous Post:
> >
> > I am working on a custom designed board with ADSP 21065L and
> > AD1881A
> > (AC'97 rev 2.1 complaint) CODEC. The interface is same as the
> > AD1819-21065L interface provided by Analog Devices. The CODEC
> > generates the BIT_CLK and in return DSP generates the SYNC. I probed
> > these things by using CRO. I am facing a problem while writing to the
> > CODEC registers. I am able to read the CODEC registers, but I am
> > unable to write to the registers. i have done a CODEC initialization
> > on another board in which ADSP 21065L processor is connected to the
> > TLV320AIC27 CODEC. In this case i could read and write to the CODEC
> > registers. Give some hints for possible causes. Does this AD1881 needs
> > some specific register initialization before it starts initializing
> > AC97 specific registers? I am specifically asking about the serial
> > configuration registers and the miscellaneous control bit registers.
> > Please note that I wish to work AD1881A in AC97 mode; not in slot16
> > mode.
> > Set one register and then read back, and then sets another one; is
> > this sequence works? What is the Codec register write latency?
> > CS0, CS1 and MODE pin are left floated in our design. Is it has any
> > effects on CODEC initialization? In AD1881 data sheet these pins are
> > left unconnected, and there is only little information for these pins.
> > But in AD1819 Codec, it is mentioned that CS0 and CS1 are tied to HIGH
> > for single Codec application.
> > Does any layout issues or power supply cause this kind of problems
> > (Consistently able to read from the registers and unable to write on
> > it. I checked the power down control status register; it shows that
> > all the 4 subsections are ready)?
> > Is anybody experiences similar problem? Please give me some hints for
> > solve this problem. Thanks.
> >
Reply by ●March 10, 20042004-03-10
>> 2. Make sure you have pulldowns on SDATA_OUT (DT) & SYNC (FS). >> > > The SDATA_OUT line is pulled down. But the Sync line not pulled > down. > The Sync shows a low value before enabling the Serial port and the > Codec.I don't remember the specific situation with the AD1881A but it some cases if these lines are high, the part will vector to a test mode.> >> 5. ID0 & ID1 select whether the AC-97 is a master or slave. Best to >> tie these pins high (assuming only one AC-97) >> > > I am not quite sure about ID0 and ID1. Are you asking to tie the > CS0 > and CS1 pins to HIGH? The CS0 and CS1 and MODE pins of the AD1881A are > left unconnected. We are using only one Codec interfaced with > ADSP21065L.I think there are internal pullups. As I recall you can probably leave them open. I still suggest the logic analyzer / DSO investigation. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.com
Reply by ●March 11, 20042004-03-11
Dear Clark,
Thanks for the information.
Is it possible to read the registers and write to the Serial
Configuration register at the test mode operation?
Currently i am helpless to check the circuit with DSO/logic analyser.
I will check the circuit again with a pull down resistor in the Sync
line.
regards
ajith
Al Clark <dsp@danvillesignal.com> wrote in message news:<Xns94A856CB45640aclarkdanvillesignal@66.133.130.30>...
> >> 2. Make sure you have pulldowns on SDATA_OUT (DT) & SYNC (FS).
> >>
> >
> > The SDATA_OUT line is pulled down. But the Sync line not pulled
> > down.
> > The Sync shows a low value before enabling the Serial port and the
> > Codec.
>
> I don't remember the specific situation with the AD1881A but it some
> cases if these lines are high, the part will vector to a test mode.
>
> >
> >> 5. ID0 & ID1 select whether the AC-97 is a master or slave. Best to
> >> tie these pins high (assuming only one AC-97)
> >>
> >
> > I am not quite sure about ID0 and ID1. Are you asking to tie the
> > CS0
> > and CS1 pins to HIGH? The CS0 and CS1 and MODE pins of the AD1881A are
> > left unconnected. We are using only one Codec interfaced with
> > ADSP21065L.
>
> I think there are internal pullups. As I recall you can probably leave
> them open.
>
> I still suggest the logic analyzer / DSO investigation.
Reply by ●March 11, 20042004-03-11
ajith_pc@yahoo.com (Ajith Kumar P C) wrote in news:18eae751.0403102022.1f3a7d84@posting.google.com:> Dear Clark, > Thanks for the information. > Is it possible to read the registers and write to the Serial > Configuration register at the test mode operation? > Currently i am helpless to check the circuit with DSO/logic analyser. > I will check the circuit again with a pull down resistor in the Sync > line. > regards > ajith >I have no idea. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- comp.dsp conference July 28 - Aug 1, 2004 details at http://www.danvillesignal.com/index.php?id=compdsp email: compdsp@danvillesignal.com Who says you can't teach an old dog a new DSP trick?
Reply by ●March 11, 20042004-03-11
Dear Al Clark and all,
I tried the Codec initialization with pulled down the Sync line
also. But the result is same as the previous case.
How can we check the Codec is entered in the Test Mode?
In our design, the CS0, CS1 and MODE pins are left unconnected. The
CS0 and CS1 and MODE pins are showing LOW value while probing.
regards
ajith
Al Clark <dsp@danvillesignal.com> wrote in message news:<Xns94A856CB45640aclarkdanvillesignal@66.133.130.30>...
> >> 2. Make sure you have pulldowns on SDATA_OUT (DT) & SYNC (FS).
> >>
> >
> > The SDATA_OUT line is pulled down. But the Sync line not pulled
> > down.
> > The Sync shows a low value before enabling the Serial port and the
> > Codec.
>
> I don't remember the specific situation with the AD1881A but it some
> cases if these lines are high, the part will vector to a test mode.
>
> >
> >> 5. ID0 & ID1 select whether the AC-97 is a master or slave. Best to
> >> tie these pins high (assuming only one AC-97)
> >>
> >
> > I am not quite sure about ID0 and ID1. Are you asking to tie the
> > CS0
> > and CS1 pins to HIGH? The CS0 and CS1 and MODE pins of the AD1881A are
> > left unconnected. We are using only one Codec interfaced with
> > ADSP21065L.
>
> I think there are internal pullups. As I recall you can probably leave
> them open.
>
> I still suggest the logic analyzer / DSO investigation.
Reply by ●March 11, 20042004-03-11
Dear Al Clark and all,
I tried the Codec initialization with pulled down the Sync line
also. But the result is same as the previous case.
How can we check the Codec is entered in the Test Mode?
In our design, the CS0, CS1 and MODE pins are left unconnected. The
CS0 and CS1 and MODE pins are showing LOW value while probing.
regards
ajith
Al Clark <dsp@danvillesignal.com> wrote in message news:<Xns94A856CB45640aclarkdanvillesignal@66.133.130.30>...
> >> 2. Make sure you have pulldowns on SDATA_OUT (DT) & SYNC (FS).
> >>
> >
> > The SDATA_OUT line is pulled down. But the Sync line not pulled
> > down.
> > The Sync shows a low value before enabling the Serial port and the
> > Codec.
>
> I don't remember the specific situation with the AD1881A but it some
> cases if these lines are high, the part will vector to a test mode.
>
> >
> >> 5. ID0 & ID1 select whether the AC-97 is a master or slave. Best to
> >> tie these pins high (assuming only one AC-97)
> >>
> >
> > I am not quite sure about ID0 and ID1. Are you asking to tie the
> > CS0
> > and CS1 pins to HIGH? The CS0 and CS1 and MODE pins of the AD1881A are
> > left unconnected. We are using only one Codec interfaced with
> > ADSP21065L.
>
> I think there are internal pullups. As I recall you can probably leave
> them open.
>
> I still suggest the logic analyzer / DSO investigation.
Reply by ●March 11, 20042004-03-11
ajith_pc@yahoo.com (Ajith Kumar P C) wrote in news:18eae751.0403110148.23ccb280@posting.google.com:> Dear Al Clark and all, > > I tried the Codec initialization with pulled down the Sync line > also. But the result is same as the previous case. > > How can we check the Codec is entered in the Test Mode? > > In our design, the CS0, CS1 and MODE pins are left unconnected. The > CS0 and CS1 and MODE pins are showing LOW value while probing.If they are low, you might be configuring the device as a slave. This would be true on the AD1819 and also the AD1881 (non A version). The AD1881A is actually less well defined in the datasheets I have. I would pull them high. Since they are NC, I would think you could do this with by soldering a wirewrap wire to the pins to the 3.3V digital supply. I don't rememeber what MODE is but I don't think it is too important. Al> > regards > ajith > > > > Al Clark <dsp@danvillesignal.com> wrote in message > news:<Xns94A856CB45640aclarkdanvillesignal@66.133.130.30>... >> >> 2. Make sure you have pulldowns on SDATA_OUT (DT) & SYNC (FS). >> >> >> > >> > The SDATA_OUT line is pulled down. But the Sync line not >> > pulled down. >> > The Sync shows a low value before enabling the Serial port and the >> > Codec. >> >> I don't remember the specific situation with the AD1881A but it some >> cases if these lines are high, the part will vector to a test mode. >> >> > >> >> 5. ID0 & ID1 select whether the AC-97 is a master or slave. Best >> >> to tie these pins high (assuming only one AC-97) >> >> >> > >> > I am not quite sure about ID0 and ID1. Are you asking to tie >> > the CS0 >> > and CS1 pins to HIGH? The CS0 and CS1 and MODE pins of the AD1881A >> > are left unconnected. We are using only one Codec interfaced with >> > ADSP21065L. >> >> I think there are internal pullups. As I recall you can probably >> leave them open. >> >> I still suggest the logic analyzer / DSO investigation. >-- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- comp.dsp conference July 28 - Aug 1, 2004 details at http://www.danvillesignal.com/index.php?id=compdsp email: compdsp@danvillesignal.com Who says you can't teach an old dog a new DSP trick?
Reply by ●March 12, 20042004-03-12
Dear Al Clark,
Thanks very much for the help. I tried with CS0 and CS1 tied
to HIGH, but still the problem is there. Today i got a reply from
Analog Devices; saying that ADSP-21065L does not support the AC'97
format. I am getting very confused.
regards
ajith
Al Clark <dsp@danvillesignal.com> wrote in message news:<Xns94A9B5CC398F0aclarkdanvillesignal@66.133.130.30>...
> ajith_pc@yahoo.com (Ajith Kumar P C) wrote in
> news:18eae751.0403110148.23ccb280@posting.google.com:
>
> > Dear Al Clark and all,
> >
> > I tried the Codec initialization with pulled down the Sync line
> > also. But the result is same as the previous case.
> >
> > How can we check the Codec is entered in the Test Mode?
> >
> > In our design, the CS0, CS1 and MODE pins are left unconnected. The
> > CS0 and CS1 and MODE pins are showing LOW value while probing.
>
> If they are low, you might be configuring the device as a slave. This
> would be true on the AD1819 and also the AD1881 (non A version). The
> AD1881A is actually less well defined in the datasheets I have.
>
> I would pull them high. Since they are NC, I would think you could do
> this with by soldering a wirewrap wire to the pins to the 3.3V digital
> supply.
>
> I don't rememeber what MODE is but I don't think it is too important.
>
> Al
>
>
>
>
>
>
>
>
> >
> > regards
> > ajith
> >
> >
> >
> > Al Clark <dsp@danvillesignal.com> wrote in message
> > news:<Xns94A856CB45640aclarkdanvillesignal@66.133.130.30>...
> >> >> 2. Make sure you have pulldowns on SDATA_OUT (DT) & SYNC (FS).
> >> >>
> >> >
> >> > The SDATA_OUT line is pulled down. But the Sync line not
> >> > pulled down.
> >> > The Sync shows a low value before enabling the Serial port and the
> >> > Codec.
> >>
> >> I don't remember the specific situation with the AD1881A but it some
> >> cases if these lines are high, the part will vector to a test mode.
> >>
> >> >
> >> >> 5. ID0 & ID1 select whether the AC-97 is a master or slave. Best
> >> >> to tie these pins high (assuming only one AC-97)
> >> >>
> >> >
> >> > I am not quite sure about ID0 and ID1. Are you asking to tie
> >> > the CS0
> >> > and CS1 pins to HIGH? The CS0 and CS1 and MODE pins of the AD1881A
> >> > are left unconnected. We are using only one Codec interfaced with
> >> > ADSP21065L.
> >>
> >> I think there are internal pullups. As I recall you can probably
> >> leave them open.
> >>
> >> I still suggest the logic analyzer / DSO investigation.
> >
>
>
>
> --
> Al Clark
> Danville Signal Processing, Inc.
> --------------------------------------------------------------------
> comp.dsp conference July 28 - Aug 1, 2004
>
> details at http://www.danvillesignal.com/index.php?id=compdsp
> email: compdsp@danvillesignal.com
>
> Who says you can't teach an old dog a new DSP trick?
